ADVANCE
INFORMATION
ENB from I/O
Control Register
I/O Pin
Output Data from
Output data
Register
Read back of
Output Data
Register
Input Data to
Input Data
Register
Internal I/O Register Data Path
Figure 5-1. GPIO Mode Block Diagram
5.1.7
I/O Address Map
CS5954AM
Table 5-1. I/O Address Map
Function
USB Endpoint 0 Address Register
USB Endpoint 0 Count Register
USB Endpoint 1 Address Register
USB Endpoint 1 Count Register
USB Endpoint 2 Address Register
USB Endpoint 2 Count Register
USB Endpoint 3 Address Register
USB Endpoint 3 Count Register
Configuration Register
Speed Control Register
Power-down Control Register
Watchdog Timer Count and Control Register
Interrupt Enable Register
Timer 0 Count Register
Timer 1 Count Register
Breakpoint Register
Extended Page 1 Map Register
Extended Page 2 Map Register
GPIO Interrupt Control Register
Output Data Register 0
Input Data Register 0
I/O Control Register 0
Output Data Register 1
Input Data Register 1
I/O Control Register 1
Extended Memory Control Register
Address
0x0120
0x0122
0x0124
0x0126
0x0128
0x012A
0x012C
0x012E
0xC006
0xC008
0xC00A
0xC00C
0xC00E
0xC010
0xC012
0xC014
0xC018
0xC01A
0xC01C
0xC01E
0xC020
0xC022
0xC024
0xC026
0xC028
0xC03A
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
R/W
R/W
Read Only
R/W
R/W
Document #: 38-08025 Rev. **
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