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CS5954AM Datasheet

  • CS5954AM

  • Cypress Semiconductor [USB Controller for NAND Flash]

  • CYPRESS

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ADVANCE
INFORMATION
4.10
Processor Control Registers
CS5954AM
The CS5954AM provides software control registers that can be used to configure the chip mode, clock control, read software
version, and software breakpoint control.
4.10.1
Configuration Register (0xC006: R/W)
The Configuration Register is used to configure the CS5954AM into the appropriate mode, and to select a clock multiplier.
[8]
D15
0
C2
0
0
0
0
1
1
1
1
D3
D14
0
D13
0
D12
0
C1
0
0
1
1
0
0
1
1
CD
D11
0
D10
0
C0
0
1
0
1
0
1
0
1
D9
0
D8
0
D7
0
PCLK
XIN
2/3*XIN
X_PCLK
2/3*XIN
4*XIN
8/3*XIN
4*XIN
8/3*XIN
D6
C2
D5
C1
D4
C0
D3
CD
RCLK
XIN
XIN
XIN
XIN
4*XIN
4*XIN
4*XIN
4*XIN
D2
M1
D1
M0
OE
0
0
0
1
0
0
1
1
D0
MD
If Clock Disable bit = 鈥?,鈥?this Clock Configuration register can no longer be modified through software writes. It is a 鈥渟ticky
bit鈥?used to lock the configuration through a write to this bit in the boot prom code.
鈥?On the CS5954AM chip set, this bit will be set to zero.
鈥?There is one mode defined in this document: general-purpose IO (GPIO) mode.
D2, D1
M1,M0:
CS5954AM modes are selected as shown here.
M1
0
0
1
1
D0
MD
M0
0
1
0
1
Mode
GPIO
Reserved
Reserved
Reserved
If Mode Disable bit = 鈥?,鈥?this Configuration register can no longer be modified through software writes. It is a 鈥渟ticky bit鈥?/div>
used to lock the configuration through a Write to this bit in the boot prom code.
[9]
D15-D7
where
PCLK
RCLK
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
is connected to the CS5954AM processor clock.
is the resulting clock that connects to other modules (i.e., USB engine).
Reserved
should be set to all zeros
OE
when
OE
= 1, the
X_PCLK
(pin 59) will become an output pin of the
PCLK
value.
When the XIN input pin is fed with a 12-MHz signal, the software should set C2 to 鈥?鈥?to enable the PLL.
X_PCLK is a bidirectional pin allowing an additional clock input for PCLK when selected or an observation pin for
PCLK when OE = 鈥?.鈥?/div>
The X_PCLK can be used as the input clock like XIN, but only when mode C2=0, C1=1, C0=0.
Upon reset, the CS5954AM BIOS will set this register equal to 0x0010 (i.e., C2=0, C1=0, C0=1, PCLK=XIN, RCLK=XIN,
OE=0, M1鈥揗0=0=GPIO Mode).
Notes:
8. D6鈥? and C2鈥? are Clock Configuration bits. These bits select the clock source. The clock may come from an outside pin (XIN or X_PCLK) or it may come from
the PLL multiplier, as indicated in the table.
9. By default, this bit will be set to zero by the CS5954AM BIOS.
Document #: 38-08025 Rev. **
Page 13 of 44

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