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CS5954AM Datasheet

  • CS5954AM

  • Cypress Semiconductor [USB Controller for NAND Flash]

  • CYPRESS

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ADVANCE
INFORMATION
4.5.2
USB Frame Number Register (0xC082: Read-only)
CS5954AM
The Frame Number Register contains the 11-bit ID number of the last SOF received by the device from the USB host.
[5]
D15
0
D14
0
D15-D11
D10-D0
4.5.3
D13
0
D12
0
Reserved
S10-S0
D11
0
D10
S10
D9
S9
D8
S8
D7
S7
D6
S6
D5
S5
D4
S4
D3
S3
D2
S2
D1
S1
D0
S0
set to all zeros.
SOF ID number of last SOF received.
USB Address Register (0xC084: R/W)
Address Register holds the USB address of the device assigned by the Host鈥搃nitialized to address 0x0000 upon power-up.
[6]
D15
0
D14
0
D15-D7
D6-D0
4.5.4
D13
0
D12
0
Reserved
A6-A0
D11
0
D10
0
D9
0
D8
0
D7
0
D6
A6
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
D0
A0
set to all zeros.
USB address of device after assignment by host.
USB Command Done Register (0xC086: Write-only)
This is the USB Command Done Register. It is only used by the control point (endpoint 0).
[7]
D15
0
D14
0
D15鈥揇1
D0
D13
0
D12
0
Reserved
E
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
E
set to all zeros
set E = 0 for successful command completion
set E = 1 for error command completion.
4.6
4.7
4.8
4.9
4.9.1
USB Endpoint 0 Control and Status Register (0xC090: R/W)
USB Endpoint 1 Control and Status Register (0xC092: R/W)
USB Endpoint 2 Control and Status Register (0xC094: R/W)
USB Endpoint 3 Control and Status Register (0xC096: R/W)
General Description for All Endpoints from Endpoint 0 to Endpoint 3
See the USB Endpoint 3 control and status register for more information.
See the USB Endpoint 3 control and status register for more information.
See the USB Endpoint 3 control and status register for more information.
The CS5954AM controller supports four endpoints. Endpoint 0 is the default pipe and is used to initialize and control the peripheral
device. It also provides access to the peripheral device鈥檚 configuration information, and supports control transfers. Endpoints 1,
2, and 3 support interrupt transfers, bulk transfers up to 64 Bytes/packet, or Isochronous transfers up to 1024 Bytes/packet size.
4.9.2
USB Endpoint Control (for Writing)
Bit Name
ARM
Enable
DIR
ISO
Stall
Zero Length
Not Defined
Function
Allows enabled transfers when set to 鈥?.鈥?Cleared to 鈥?鈥?when transfer is complete.
When set to 鈥?鈥?it allows transfers to this endpoint. When set to 鈥?鈥?USB transactions are ignored.
If enable = 鈥?鈥?and Arm = 鈥?鈥?the endpoint will return NAK to USB transmissions.
When set to 鈥?鈥?it transmits to Host (IN). When 鈥?鈥?receive from Host (OUT).
When set to 鈥?鈥?it allows Isochronous mode for this endpoint.
When set to 鈥?鈥?it sends Stall in response to next request on this endpoint.
When set to 鈥?鈥?it sends a zero length packet.
Set to logic 鈥?鈥漵.
Each of the endpoint control registers, when written, have the following functions assigned.
Bit Position
D0
D1
D2
D3
D4
D5
D6鈥揇15
Notes:
5. The CS5954AM BIOS uses this register to detect USB activity for the internal idle task.
6. The CS5954AM BIOS modifies this register upon receiving the SET_ADDRESS from the host. (See [Ref. 3] Universal Serial Bus Specification v2.0 sec. 9 for
more information.)
Document #: 38-08025 Rev. **
Page 11 of 44

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