CS5351
t sclkh t sclkl
SCLK input
SCLK output
t msl
r
t sl rd
LRCK input
t sclkw
LRCK
output
t sd
o
SDOUT
MSB
MSB-1
SDOUT
t lrdss
MSB
MSB-1
t dss
MSB-2
Figure 16. Master Mode, Left Justified SAI
Figure 17. Slave Mode, Left Justified SAI
t sclkh t sclkl
SCLK input
t mslr
LRCK output
t
sdo
SCLK
output
t sclkw
LRCK input
t dss
SDOUT
MSB
SDOUT
MSB
MSB-1
Figure 18. Master Mode, I
2
S SAI
Figure 19. Slave Mode, I
2
S SAI
LRCK
t setup
OVFL
t hold
Figure 20. OVFL Output Timing
DS565PP2
19