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CS5340-DZZ Datasheet

  • CS5340-DZZ

  • Cirrus Logic [101 dB, 192kHz, MULTI-BIT AUDIO A/D CONVERTER...

  • CIRRUS

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CS5340
4.4
Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and config-
uration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the
minimum specified operating voltages to prevent power glitch related issues.
4.5
Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the
filter. However, there is no rejection for input signals which are multiples of the input sampling frequency
(n
脳
6.144 MHz), where n=0,1,2,... Refer to Figure 21 which shows the suggested filter that will attenuate any noise
energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capac-
itors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can
degrade signal linearity.
634
鈩?/div>
V
A
470 pF
COG
100k
鈩?/div>
-
+
COG
2200 pF
91
鈩?/div>
C S5340 A INL
4.7 uF
A INL
100k
鈩?/div>
VA
100k
鈩?/div>
4.7 uF
A INR
100k
鈩?/div>
+
-
470 pF
COG
COG
2200 pF
634
鈩?/div>
91
鈩?/div>
CS 5340 A INR
Figure 21. CS5340 Recommended Analog Input Buffer
4.6
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5340 requires careful attention to power supply and grounding arrange-
ments if its potential performance is to be realized. Figure 17 shows the recommended power arrangements, with
VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply
or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from
VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being
the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid un-
wanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.01 碌F, must be
positioned to minimize the electrical path from FILT+ and REF_GND. The CDB5340 evaluation board demonstrates
the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only
to CMOS inputs.
20
DS601PP2

CS5340-DZZ 產(chǎn)品屬性

  • 96

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器

  • -

  • 24

  • 200k

  • 串行

  • 2

  • -

  • 模擬和數(shù)字

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-TSSOP（0.173"，4.40mm 寬）

  • 16-TSSOP

  • 管件

  • 2 個單端，單極

  • 598-1544-ND - BOARD EVAL FOR CS5340 STEREO ADC

  • 598-1686

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