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CS5340-DZZ Datasheet

  • CS5340-DZZ

  • Cirrus Logic [101 dB, 192kHz, MULTI-BIT AUDIO A/D CONVERTER...

  • 460.33KB

  • CIRRUS

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CS5340
4 APPLICATIONS
4.1
Single, Double, and Quad Speed Modes
The CS5340 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be determined
by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.
Speed Mode
Single Speed Mode
Double Speed Mode
Quad Speed Mode
MCLK/LRCK
Ratio
512x
256x
256x
128x
128x
64x*
Output Sample Rate Range (kHz)
43 - 54
2 - 54
86 - 108
50 - 108
172 - 200
100 - 200
* Quad Speed Mode, 64x only available in Master Mode.
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)
4.2
Operation as Either a Clock Master or Slave
The CS5340 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK pins are
outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the LRCK and SCLK
pins are inputs and require the left/right and serial clocks to be externally generated. The selection of clock master
or slave is made via the Mode pins as shown in Table 2.
M1 (Pin 16)
0
0
1
1
M0 (Pin 1)
0
1
0
1
MODE
Clock Master, Single Speed Mode
Clock Master, Double Speed Mode
Clock Master, Quad Speed Mode
Clock Slave, All Speed Modes
Table 2. CS5340 Mode Control
DS601PP2
17

CS5340-DZZ 產(chǎn)品屬性

  • 96

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器

  • -

  • 24

  • 200k

  • 串行

  • 2

  • -

  • 模擬和數(shù)字

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-TSSOP（0.173"，4.40mm 寬）

  • 16-TSSOP

  • 管件

  • 2 個(gè)單端，單極

  • 598-1544-ND - BOARD EVAL FOR CS5340 STEREO ADC

  • 598-1686

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