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CS5340-CZZ Datasheet

  • CS5340-CZZ

  • Cirrus Logic [101 dB, 192kHz, MULTI-BIT AUDIO A/D CONVERTER...

  • 430.93KB

  • CIRRUS

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CS5340
4.7
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure
synchronous sampling, the MCLK and LRCK must be the same for all of the CS5340鈥檚 in the system. If only one
master clock source is needed, one solution is to place one CS5340 in Master mode, and slave all of the other
CS5340鈥檚 to the one master. If multiple master clock sources are needed, a possible solution would be to supply all
clocks from the same external source and time the CS5340 reset with the inactive (falling) edge of MCLK. This will
ensure that all converters begin sampling on the same clock edge.
4.8
Capacitor Size on the Reference Pin (FILT+)
The CS5340 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decou-
pling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger capacitor val-
ues used to optimize low frequency distortion performance.
1 uF
2.2 uF
3.3 uF
4.7 uF
5.6 uF
6.8 uF
10 uF
22 uF
47 uF
100 uF
Figure 22. CS5340 THD+N versus Frequency
DS601PP2
21

CS5340-CZZ 產(chǎn)品屬性

  • 96

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器

  • -

  • 24

  • 200k

  • 串行

  • 2

  • -

  • 單電源

  • -10°C ~ 70°C

  • 表面貼裝

  • 16-TSSOP（0.173"，4.40mm 寬）

  • 16-TSSOP

  • 管件

  • 2 個(gè)單端，單極

  • 598-1544-ND - BOARD EVAL FOR CS5340 STEREO ADC

  • 598-1081-5

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