最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

CS5336 Datasheet

  • CS5336

  • Cirrus Logic [16-Bit, Stereo A/D Converters for Digital Aud...

  • CIRRUS

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

CDB5336,8,9
VD+
R8
13
SMODE
20 k
1
A-to-B
Enable
13 B-to-A
Enable
11
B1
10
B2
VCC
U9
VD+
14
7
GND
3
A1
A2
4
5
B4
A3
R10
20 k
CS8402
Pin 6
4
5336/38
5337/39
P4
15
SCLK
17
FSYNC
14
L/R
16
SDATA
4
5
U8B
SCLK
FSYNC
L/R
SDATA
SDATA
VD+
0.1 uF
C20
SCLK
FSYNC
L/R
74HC243
9 B3
6
A4
8
6
9
U8C
10
74HC08
R9
20 k
8
SDATA
U7B
3
Pin 11
U4, U5
595鈥檚
Figure 5. Serial Output Interface
on the rising edge of SCLK and shifted into the
16-bit shift register formed by U4 and U5 on
SCLK鈥檚 falling edge. After all data bits for the
selected channel have been shifted into U4 and
U5 the data is latched onto P1 by a delayed ver-
sion of FSYNC.
P5 selects the channel whose output data will be
converted to parallel form and presented on P1.
With P5 in the "B" (both) position, parallel data
from one channel will be presented first with
data from the other channel presented sub-
sequently. In the "L" (left) position, only left
channel conversions will be presented, while in
the "R" (right) position only right channel con-
versions are presented.
Two interface mechanisms are provided for read-
ing the data from this port. With the first, the
edges of L/R may be used to clock the parallel
data into the digital signal processor. (Set jumper
P2 into the L/R position.) Alternatively, a hand-
shake protocol implemented with DACK and
DRDY may be used to transfer data to the signal
DS23DB5
processor. (Set jumper P2 to the DRDY posi-
tion.) The fall of DRDY informs the digital
signal processor that a new data word is avail-
able. The processor then reads the port and
acknowledges the transfer by asserting DACK.
Note that DRDY will not be asserted again un-
less DACK is momentarily brought high
although new data will continue to be latched
onto the port.
Digital Audio Standard Interface
Included on the evaluation board is a CS8402
Digital Audio Line Driver. This device can im-
plement AES/EBU, S/PDIF and EIAJ CP-340
interface standards. Figure 4 shows the sche-
matic for the CS8402. P3 allows the C, U and V
bits to be driven from external logic using the
CBL output for block synchronization. SW2 pro-
vides 8 DIP switches to select various modes
and bits for the CS8402. Table 3 lists the settings
for the professional mode which is the default
setting for the evaluation board from the factory.
The third switch selects between professional
3-65

CS5336 PDF文件相關(guān)型號

CS5336-BP

CS5336相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！