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CS5336 Datasheet

  • CS5336

  • Cirrus Logic [16-Bit, Stereo A/D Converters for Digital Aud...

  • 682.31KB

  • CIRRUS

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CS5336, CS5338, CS5339
ZEROL, ZEROR - Zero Level Inputs for Left and Right Channels, PINS 3, 26.
Analog zero level inputs for the left and right channels. The levels present on these pins
can be used as zero during the offset calibration cycle. Normally connected to AGND,
optionally through networks matched to the analog input networks.
Analog Outputs
VREF - Voltage Reference Output, PIN 28.
Nominally -3.68 volts. Normally connected to a 0.1碌F ceramic capacitor in parallel with a
10碌F or larger electrolytic capacitor. Note the negative output polarity.
Digital Inputs
ICLKA - Analog Section Input Clock, PIN 23.
This clock is internally divided by 2 to set the modulators鈥?sample rate. Sampling rates,
output rates, and digital filter characteristics scale to ICLKA frequency. ICLKA frequency
is 128 X the output word rate. For example, 6.144 MHz ICLKA corresponds to an output
word rate of 48 kHz per channel. Normally connected to OCLKD.
ICLKD - Digital Section Input Clock, PIN 20.
This is the clock which runs the digital filter. ICLKD frequency is determined by the
required output word rate and by the CMODE pin. If CMODE is low, ICLKD frequency
should be 256 X the desired output word rate. If CMODE is high, ICLKD should be
384 X the desired output word rate. For example, with CMODE low, ICLKD should be
12.288 MHz for an output word rate of 48 kHz. This clock also generates OCLKD,
which is always 128 X the output word rate.
APD - Analog Power Down, PIN 6.
Analog section power-down command. When high, the analog circuitry is in power-down
mode. APD is normally connected to DPD when using the power down feature. If power
down is not used, then connect APD to AGND.
DPD - Digital Power Down, PIN 10
Digital section power-down command. Bringing DPD high puts the digital section into
power-down mode. Upon returning low, the ADC starts an offset calibration cycle. This
takes 4096 L/R periods (85.33 ms with a 12.288 MHz ICLKD). DCAL is high during the
calibrate cycle and goes low upon completion. DPD is normally connected to APD when
using the power down feature. A calibration cycle should always be initiated after
applying power to the supply pins.
ACAL - Analog Calibrate, PIN 7.
Analog section calibration command. When high, causes the left and right channel
modulator inputs to be internally connected to ZEROL and ZEROR inputs respectively.
May be connected to DCAL.
DS23F1
3-55

CS5336 PDF文件相關(guān)型號

CS5336-BP

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