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CS5317-KP Datasheet

  • CS5317-KP

  • Cirrus Logic [16-Bit, 20 kHz Oversampling A/D Converter]

  • CIRRUS

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CDB5317
CLKOUT
DATA
DOUT
Note: For a complete description of serial timing see the CS5317 Data Sheet
Figure 4 Serial Data Timing
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
two modes which use the phase locked loop will
require appropriate low pass filter components on
the Evaluation Board. The low pass filter compo-
nents help determine the PLL control loop
response, including its bandwidth and stability
and therefore directly affect the transient response
of the PLL control loop. Appropriate filter compo-
nents should be installed if a particular dynamic
response to changes of the CLKIN signal is de-
sired.
The filter components which are installed on the
board have been chosen for the following parame-
ters: MODE: CLKG2; CLKIN: 7,200; N=512;
damping factor: 1.0; Control loop -3 dB band-
width: 2262 radians/second. These parameters
yield R as 10 k
鈩?/div>
and C as 0.22
碌F
for the filter
components.
The analog signal to be digitized is input to the
AIN BNC connector. The digital output words
from the CS5317 are buffered by HEX inverters
as shown in Figure 3. The buffered versions of
the CLKOUT and DATA signals are available on
the header connector P1 in Figure 6. The serial
data signals out of the CS5317 are illustrated in
Figure 4. If remote control of the DOE line is
desired, the trace on the PC Board can be opened
and a wire connection can be soldered to the DOE
input line. Remote control of the RST line of the
CS5317 is also available if desired.
Figures 5 and 6 illustrate the serial to parallel shift
registers including timing information. The DATA
output signal from the CS5317 is input to the data
input of the shift register. An inverted version of
the CLKOUT signal is used to clock the DATA
into the shift registers. The two 8-bit shift register
ICs also include output latches. The rising edge
Serial Data
Shifting Out
Parallel Data (D0-D15) Valid
Serial Data
Shifting Out
Parallel Data Valid
DATA
DOUT
DRDY
DACK
Figure 5. Parallel Data Timing
DS27DB3
29

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