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CS4953 Datasheet

  • CS4953

  • Cirrus Logic [NTSC/PAL Digital Video Encoder]

  • CIRRUS

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CS4952/53
GPIO_CTRL_REG [7:0] bits are cleared. In GPIO
input mode, the CS4952/53 will latch the data on
the PDAT [7:0] pins into the corresponding bit lo-
cations of GPIO_DATA_REG when it detects reg-
ister address 0x0A through the I
2
C interface. A
detection of address 0x0A can happen in two ways.
The first and most common way this will happen is
when address 0x0A is written to the CS4952/53 via
its I
2
C interface. The second method for detecting
address 0x0A is implemented by accessing register
address 0x09 through I
2
C. In I
2
C host interface op-
eration, the CS4952/53 register address pointer will
auto-increment to address 0x0A after an address
0x09 access.
The GPIO port PDAT [7:0] pins are configured for
output operation when the corresponding
GPIO_CTRL_REG [7:0] bits are set. In GPIO out-
put mode, the CS4952/53 will output the data in
GPIO_DATA_REG [7:0] bit locations onto the
corresponding PDAT [7:0] pins when it detects a
register address 0x0A through the I
2
C interface.
COLOR
White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
Cb
0
-84
+28
-56
+56
-28
+84
0
Cr
0
+14
-84
-70
+70
+84
-14
0
Y
+180
+162
+131
+112
+84
+69
+35
+16
Table 4. Internal Color Bar Values
(8-bit values, Cb/Cr are in 2鈥檚 complement format)
Interrupts
In order to better support precise video mode
switches and to establish a software/hardware
handshake with the closed caption insertion block
the CS4952/3 is equipped with an interrupt pin
named INT. The INT pin is active high. There are
three interrupt sources: VSYNC, Line 21 and Line
284. Each interrupt can be individually disabled
with the INT_EN register. Each interrupt is also
cleared via writing a one to the corresponding
INT_CLR register bits. The three individual inter-
rupts are ORed together to generate an interrupt
signal which is presented on the INT output pin. If
an interrupt has occurred, it cannot be eliminated
with a disable, it must be cleared.
ANALOG
Analog Timing
All CS4952/3 analog timing and sequencing is de-
rived from the 27 MHz clock input. The analog out-
puts are controlled internally by the video timing
generator in conjunction with master and slave tim-
ing. The video output signals perform accordingly
for NTSC, PAL specifications and both modes again
but with progressive scan non-interlaced video out-
put.
Being that the CS4952/3 is almost entirely a digital
circuit, great care has been taken to guarantee ana-
log timing and slew rate performance as specified
in the NTSC and PAL analog specifications. Refer-
ence the Analog Parameters section of this data
sheet for exact performance parameters.
General Purpose I/O Port
The CS4952/53 has a GPIO port and register which
is available when the device is configured for I
2
C
host interface operation. In I
2
C host interface
mode, the PDAT [7:0] pins are unused by the host
interface and they may operate independently as in-
put or output pins for the GPIO_DATA_REG reg-
ister (0x0A). The CS4952/53 also contains the
GPIO_CTRL_REG Register (0x09) which is used
to configure the GPIO pins for input or output op-
eration.
The GPIO port PDAT [7:0] pins are configured for
input operation when the corresponding
24
DS223PP2

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