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CS493122-CL Datasheet

  • CS493122-CL

  • Cirrus Logic [Multi-Standard Audio Decoder Family]

  • CIRRUS

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CS49300 Family DSP
12. PIN DESCRIPTIONS
VD1
DGND1
AUDATA3, XMT958
WR,DS,EMWR,GPIO10
RD,R/W,EMOE,GPIO11
A1, SCDIN
A0, SCCLK
DATA7,EMAD7,GPIO7
DATA6,EMAD6,GPIO6
DATA5,EMAD5,GPIO5
DATA4,EMAD4,GPIO4
VD2
DGND2
DATA3,EMAD3,GPIO3
DATA2,EMAD2,GPIO2
DATA1,EMAD1,GPIO1
DATA0,EMAD0,GPIO0
CS
SCDIO, SCDOUT,PSEL,GPIO9
ABOOT, INTREQ
EXTMEM, GPIO8
SDATAN1
6 5 4
7
8
9
10
11
12
13
14
15
16
17
18 19 20
3 2 1 44 43 42 41 40
39
38
37
36
35
CS493XX-CL
34
44-pin PLCC
33
32
Top View
31
30
29
21 22 23 24 25 26 27 28
MCLK
SCLK
LRCLK
AUDATA0
AUDATA1
AUDATA2
DC
DD
RESET
AGND
VA
FILT1
FILT2
CLKSEL
CLKIN
CMPREQ, LRCLKN2
CMPCLK, SCLKN2
CMPDAT, SDATAN2, RCV958
LRCLKN1
SCLKN1, STCCLK2
DGND3
VD3
VA鈥擜nalog Positive Supply: Pin 34
Analog positive supply for clock generator. Nominally +2.5 V.
AGND鈥擜nalog Supply Ground: Pin 35
Analog ground for clock generator PLL.
VD1, VD2, VD3鈥擠igital Positive Supply: Pins 1, 12, 23
Digital positive supplies. Nominally +2.5 V.
DGND1, DGND2, DGND3鈥擠igital Supply Ground: Pins 2, 13, 24
Digital ground.
FILT1鈥擯hase-Locked Loop Filter: Pin 33
Connects to an external filter for the on-chip phase-locked loop.
FILT2鈥擯hase Locked Loop Filter: Pin 32
Connects to an external filter for the on-chip phase-locked loop.
CLKIN鈥擬aster Clock Input: Pin 30
CS493XX clock input. When in internal clock mode (CLKSEL == DGND), this input is
connected to the internal PLL from which all internal clocks are derived. When in external
clock mode (CLKSEL == VD), this input is connected to the DSP clock.
INPUT
80
DS339PP4

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