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CS493122-CL Datasheet

  • CS493122-CL

  • Cirrus Logic [Multi-Standard Audio Decoder Family]

  • 1340.73KB

  • CIRRUS

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CS49300 Family DSP
DAO Data Format Of
AUDATA0, 1, 2 (or AUDATA0
B Value
for Multichannel Modes)
22
Multichannel (2 channel)
20-bit Left Justified
(SCLK must be at least
128Fs
for this mode)
(Configuration of AUDATA3 as S/PDIF
(IEC60958) or Digital Audio in the
format of I
2
S or Left Justified is
covered in AN162 and AN163)
24
Multichannel (4 channel)
20-bit Left Justified
(SCLK must be at least
128Fs
for this mode)
(Configuration of AUDATA3 as S/PDIF
(IEC60958) or Digital Audio in the
format of I
2
S or Left Justified is
covered in AN162 and AN163)
3
Multichannel (6 channel)
24-bit Left Justified
(SCLK must be at least
256Fs
for this mode)
(Configuration of AUDATA3 as S/PDIF
(IEC60958) or Digital Audio in the
format of I
2
S or Left Justified is
covered in AN162 and AN163)
32
Multichannel (2 channel)
24-bit Left Justified
(SCLK must be at least
128Fs
for this mode)
(Configuration of AUDATA3 as S/PDIF
(IEC60958) or Digital Audio in the
format of I
2
S or Left Justified is
covered in AN162 and AN163)
Hex
Message
0x80027F
0xFC7FFF
0x80017F
0x018000
0x80027C
0xF01F00
0x80017C
0x001300
0x80027F
0xFC7FFF
0x80017F
0x010000
0x80027C
0xF01F00
0x80017C
0x001300
0x80027F
0xFC7FFF
0x80027C
0xF01F00
0x80027D
0xF01F00
0x80027E
0xF01F00
0x80027F
0xFC7FFF
0x80027C
0xF01F00
0x80017F
0x018000
C Value
MCLK Frequency
0
256Fs
(default)
1
512Fs
2
128Fs
3
384Fs
(SCLK must be 64Fs in this
mode and MCLK must be an
input)
Hex
Message
0x80027F
0xFFE7FF
0x80027F
0xFFE7FF
0x80017F
0x001000
0x80027F
0xFFE7FF
0x80017F
0x001800
0x80027F
0xFFE7FF
0x80017F
0x000800
Table 24. Output MCLK Configuration
(Parameter C)
D Value
SCLK Frequency
0
64Fs
(default)
Hex
Message
0x80027F
0xFFF8FF
0x80017F
0x000100
0x80027F
0xFFF8FF
0x80017F
0x000200
0x80027F
0xFFF8FF
0x80017F
0x000300
1
128Fs
2
256Fs
34
0x80027F
0xFC7FFF
0x80017F
0x010000
(Configuration of AUDATA3 as S/PDIF
0x80027C
(IEC60958) or Digital Audio in the
0xF01F00
format of I
2
S or Left Justified is
covered in AN162 and AN163)
Multichannel (4 channel)
24-bit Left Justified
(SCLK must be at least
128Fs
for this mode)
Table 25. Output SCLK Configuration
(Parameter D)
E Value
SCLK Polarity
0
Data Valid on Rising Edge
(default) (clocked out on falling)
1
Data Valid on Falling Edge
(clocked out on rising)
Hex
Message
0x80027F
0xF7FFFF
0x80017F
0x080000
Table 23. Output Data Format Configuration
(Parameter B) (Continued)
Table 26. Output SCLK Polarity Configuration
(Parameter E)
DS339PP4
77

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