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CS493122-CL Datasheet

  • CS493122-CL

  • Cirrus Logic [Multi-Standard Audio Decoder Family]

  • CIRRUS

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CS49300 Family DSP
1.5. Switching Characteristics 鈥?RESET
(T
A
= 25
擄C;
VA, VD[3:1] = 2.5 V
鹵5%;
Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 20 pF)
Parameter
RESET minimum pulse width low (-CL)
RESET minimum pulse width low (-IL)
All bidirectional pins high-Z after RESET low
Configuration bits setup before RESET high
Configuration bits hold after RESET high
(Note 1)
(Note 1)
(Note 2)
Symbol
T
rstl
T
rstl
T
rst2z
T
rstsu
T
rsthld
Min
100
530
-
50
15
Max
-
-
50
-
-
Unit
碌s
碌s
ns
ns
ns
Notes: 1. The minimum RESET pulse listed above is valid only when using the recommended pull-up/pull-down
resistors on the RD, WR, PSEL and ABOOT mode pins. For Rev. D and older parts, pull-up/pull-down
resistors may be 4.7 k or 3.3 k. For Rev. E and newer parts, pull-up/pull-down resistors must be 3.3 k.
2. This specification is characterized but not production tested.
RESET
RD, W R,
P S E L, A B O O T
A ll B idirectional
P ins
T
rst2z
T
rstl
T
rstsu
T
rsthld
Figure 1. RESET Timing
1.6. Switching Characteristics 鈥?CLKIN
(T
A
= 25
擄C;
VA, VD[3:1] = 2.5 V
鹵5%;
Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 20 pF)
Parameter
CLKIN period for internal DSP clock mode
CLKIN high time for internal DSP clock mode
CLKIN low time for internal DSP clock mode
Symbol
T
clki
T
clkih
T
clkil
Min
35
18
18
Max
3800
Unit
ns
ns
ns
C L K IN
T
clkih
T
clki
T
clkil
Figure 2. CLKIN with CLKSEL = VSS = PLL Enable
DS339PP4
7

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