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CS493122-CL Datasheet

  • CS493122-CL

  • Cirrus Logic [Multi-Standard Audio Decoder Family]

  • CIRRUS

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CS49300 Family DSP
about how to control the GPIO pins of the DSP via
messaging to the SPI or I
2
C port.
to external SRAM, such as decoding of AAC
Multichannel streams, which have a 5.1 channel
output. These applications require that the DSP has
real-time access to 70nS (or faster) 32 Kilobyte
SRAM. The 128 Kilobyte SRAM on the
CDB49300-MEMA.0 is made accessible by the
DSP when the host drives uC18 high. The external
256 Kilobyte EPROM is accessible to the DSP
when the host controller drives uC18 low. The with
uC15, uC16, and uC17 lines are used to page
between the various code images.
8.8. CDB49300-MEMA.0
The CDB49300-MEMA.0 is an external memory
adapter card designed for use with the
CDB4923/CDB4930 REV-A.0 Evaluation Board.
The schematic for the CDB49300-MEMA.0 is
shown in Figure 42. This board is an example of
one possible external memory configuration.
In addition to autobooting from external EPROM,
certain application codes require real-time access
DS339PP4
65

CS493122-CL PDF文件相關(guān)型號

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