最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

CS493122-CL Datasheet

  • CS493122-CL

  • Cirrus Logic [Multi-Standard Audio Decoder Family]

  • 1340.73KB

  • CIRRUS

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

CS49300 Family DSP
6.2.1.1.Writing a Byte in Intel Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
must insure that all of the timing constraints of the
Intel Parallel Host Mode Write Cycle are met.
The flow diagram shown in
Figure 24
illustrates
the sequence of events that define a one-byte write
in Intel mode. The protocol presented in
Figure 24
will now be described in detail.
1) The host must first drive the A1 and A0 register
address pins of the CS493XX with the address
of the desired Parallel I/O Register.
Host Message:
Host Control:
PCMDATA:
CMPDATA:
A[1:0]==00b.
A[1:0]==01b.
A[1:0]==10b.
A[1:0]==11b.
the host ends the write cycle by driving the CS
and WR pins high.
6.2.1.2.Reading a Byte in Intel Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
must insure that all of the timing constraints of the
Intel Parallel Host Mode Read Cycle are met.
The flow diagram shown in
Figure 25
illustrates
the sequence of events that define a one-byte read
in Intel mode. The protocol presented in
Figure 25
will now be described in detail.
1) The host must first drive the A1 and A0 register
address pins of the CS493XX with the address
of the desired Parallel I/O Register. Note that
only the Host Message register and the Host
Control register can be read.
Host Message:
Host Control:
A[1:0]==00b.
A[1:0]==01b.
2) The host then indicates that the selected register
will be written. The host initiates a write cycle
by driving the CS and WR pins low.
3) The host drives the data byte to the DATA[7:0]
pins of the CS493XX.
4) Once the setup time for the write has been met,
ADDRESS A PARALLEL I/O REGISTER
(A[1:0] SET APPROPRIATELY
2) The host now indicates that the selected register
will be read. The host initiates a read cycle by
driving the CS and RD pins low.
3) Once the data is valid, the host can read the
value of the selected register from the
DATA[7:0] pins of the CS493XX.
ADDRESS A PARALLEL I/O REGISTER
(A[1:0] SET APPROPRIATELY
C S (LO W )
W R (LO W )
C S (LO W )
R D (LO W )
WRITE BYTE TO
DATA [7:0]
READ BYTE FROM
DATA [7:0]
CS (HIGH)
WR (HIGH)
CS (HIGH)
RD (HIGH)
Figure 24. Intel Mode, One-Byte Write Flow Diagram
Figure 25. Intel Mode, One-Byte Read Flow Diagram
DS339PP4
44

CS493122-CL PDF文件相關(guān)型號(hào)

CS493292-CL,CS493302-CL

CS493122-CL相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門(mén)IC型號(hào)推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買(mǎi)家服務(wù)：
賣(mài)家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！