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CS493122-CL Datasheet

  • CS493122-CL

  • Cirrus Logic [Multi-Standard Audio Decoder Family]

  • 1340.73KB

  • CIRRUS

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40
I
2
C Stop
D7
D6
D5
D4
D3
D2
D1
D0
AC K D 7
D6
D5
D4
D3
D2
D1
D0
AC K D7
D6
D5
D4
D3
D2
D1
D0
A CK
I
2
C Start
SCCLK
SCDIO
A D6 A D5 A D 4 A D3 A D 2 A D 1 A D 0 R/W A C K
I
2
C W rite Functional Tim ing
I
2
C Start
I
2
C Stop
SCCLK
AC K
D7
D6
D5
D4
D3
D2
D1
D0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
NA CK
SCDIO
AD 6 AD 5
A D4 A D3 A D 2 A D1 A D0 R /W
INTREQ
Note 1
Note 2
Note 3
Note 4
Note 5
I
2
C Read Functional Tim ing
Notes: 1. The ACK for the address byte is driven by the CS493XX.
2. The ACKs for the data bytes being read from the CS493XX should be driven by the host.
3. INTREQ is guaranteed to stay LOW until the rising edge of SCCLK for bit D0 of the last byte
to be transferred out of the CS493XX.
4. A NACK should be sent by the host after the last byte to indicate the end of the read cycle.
5. INTREQ is guaranteed to stay HIGH until the next rising edge of SCCLK (for the ACK/NACK
bit) at which point it may go LOW again if there is new data to be read. The condition of
INTREQ going LOW at this point should be treated as a new read condition. After a stop
condition, a new start condition followed by an address byte should be sent.
CS49300 Family DSP
DS339PP4
Figure 24. I
2
C
廬
Timing

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