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CS493122-CL Datasheet

  • CS493122-CL

  • Cirrus Logic [Multi-Standard Audio Decoder Family]

  • CIRRUS

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CS49300 Family DSP
acknowledge is not sent by the CS493XX, a
stop condition should be issued and the read
sequence should be restarted.
5) The data is ready to be clocked out on the
SCDIO line at this point. Data clocked out by
the host is valid on the rising edge of SCCLK
and data transitions occur on the falling edge of
SCCLK.
6) If INTREQ is still low after a byte transfer, an
acknowledge (SCDIO clocked low by SCCLK)
must be sent by the host to the CS493XX and
another byte should be clocked out of the
CS493XX. Please see the discussion below for
a complete description of INTREQ鈥檚 behavior.
7) When INTREQ has risen, a no acknowledge
should be sent by the host (SCDIO clocked
high by the host) to the CS493XX. This,
followed by an I
2
C
廬
stop condition (SCDIO
raised, while SCCLK is high) signals an end of
read to the CS493XX.
Understanding the role of INTREQ is important for
successful communication. INTREQ is guaranteed
to remain low (once it has gone low), until the
rising edge of SCCLK for the last bit of the last byte
to be transferred out of the CS493XX (i.e. the
rising edge of SCCLK before the ACK SCCLK). If
there is no more data to be transferred, INTREQ
will go high at this point. After going high,
INTREQ is guaranteed to stay high until the next
rising edge of SCCLK (i.e. it will stay high until the
rising edge of SCCLK for the ACK/NACK bit).
This end of transfer condition signals the host to
end the read transaction by clocking the last data bit
out of the CS493XX and then sending a no
acknowledge to the CS493XX to signal that the
read sequence is over. At this point the host should
send an I
2
C
廬
stop condition to complete the read
sequence. If INTREQ is still low after the rising
edge of SCCLK on the last data bit of the current
byte, the host should send an acknowledge and
continue reading data from the serial control port.
It should be noted that all data should be read out of
the serial control port during one cycle or a loss of
data will occur. In other words, all data should be
read out of the chip until INTREQ signals the last
byte by going high as described above. Please see
Section 6.1.3, 鈥淚NTREQ Behavior: A Special
Case鈥?on page 39
for a more detailed description of
INTREQ behavior.
INTREQ
LOW?
YES
SEND I
2
C START:
DROP SCDIO LOW
WHILE SCCLK IS HIGH
NO
WRITE ADDRESS BYTE
WITH MODE BIT
SET TO 1 FOR READ
GET ACK
READ DATABYTE
YES
INTREQ
STILL LOW?
NO
SEND NACK
SEND ACK
SEND I
2
C STOP:
RISING EDGE OF SCDIO
WHILE SCLK IS HIGH
Figure 23. I
2
C
廬
Read Flow Diagram
38
DS339PP4

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