CS49300 Family DSP
MCLK (Input)
T
mclk
SCLK (Output)
T
sdmi
MCLK (Output)
T
mclk
SCLK (Output)
T
sdmo
MASTER MODE
SCLK
T
sclk
T
lrds
LRCLK
T
a d s m
AUDATA2:0
SLAVE MODE
SCLK
T
lrts
LRCLK
T
adss
AUDATA2:0
T
sclk
T
stlr
Figure 12. Digital Audio Output Data, Input and Output Clock Timing
20
DS339PP4