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CS493122-CL Datasheet

  • CS493122-CL

  • Cirrus Logic [Multi-Standard Audio Decoder Family]

  • 1340.73KB

  • CIRRUS

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CS49300 Family DSP
1.12. Switching Characteristics 鈥?CMPDAT, CMPCLK
(T
A
= 25
擄C;
VA, VD[3:1] = 2.5 V
鹵5%;
Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 20 pF)
Parameter
Serial compressed data clock CMPCLK period
CMPDAT setup before CMPCLK high
CMPDAT hold after CMPCLK high
Symbol
T
cmpclk
T
cmpsu
T
cmphld
Min
-
5
3
Max
27
-
-
Unit
MHz
ns
ns
CM P CL K
CM P DA T
T
cm ps u
T
cm p clk
Figure 10. Serial Compressed Data Timing
T
cm p hld
1.13. Switching Characteristics 鈥?Parallel Data Input
(T
A
= 25
擄C;
VA, VD[3:1] = 2.5 V
鹵5%;
Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 20 pF)
Parameter
CMPCLK Period
DATA[7:0] setup before CMPCLK high
DATA[7:0] hold after CMPCLK high
Symbol
T
cmpclk
T
cmpsu
T
cmphld
Min
4*DCLK + 10
10
10
Max
Unit
ns
ns
ns
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can
be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/4 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLK == 100ns
DCLK == 65 MHz after boot, i.e. DCLK == 15.4ns
It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.
C M P C LK
D A T A [7:0]
T
cm psu
T
cm pclk
T
cm phld
Figure 11. Parallel Data Timing (when not in a parallel control mode)
18
DS339PP4

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