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CS493122-CL Datasheet

  • CS493122-CL

  • Cirrus Logic [Multi-Standard Audio Decoder Family]

  • CIRRUS

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CS49300 Family DSP
1.11. Switching Characteristics 鈥?Digital Audio Input
(T
A
= 25
擄C;
VA, VD[3:1] = 2.5 V
鹵5%;
Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 20 pF)
Parameter
SCLKN1(2) period for both Master and Slave mode
SCLKN1(2) duty cycle for Master and Slave mode
Master Mode
LRCLKN1(2) delay after SCLKN1(2) transition
SDATAN1(2) setup to SCLKN1(2) transition
SDATAN1(2) hold time after SCLKN1(2) transition
Slave Mode
Time from active edge of SCLKN1(2) to LRCLKN1(2) transition
Time from LRCLKN1(2) transition to SCLKN1(2) active edge
SDATAN1(2) setup to SCLKN1(2) transition
SDATAN1(2) hold time after SCLKN1(2) transition
(Note 4)
(Note 4)
(Note 1)
(Note 1)
(Note 1, 2)
(Note 3)
(Note 4)
(Note 4)
(Note 5)
T
stlr
T
lrts
T
sdsus
T
sdhs
10
10
5
5
-
-
-
-
ns
ns
ns
ns
T
lrds
T
sdsum
T
sdhm
-
10
5
10
-
-
ns
ns
ns
Symbol
T
sclki
Min
40
45
Max
-
55
Unit
ns
%
Notes: 1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS493XX driving LRCLKN1(2) and SCLKN1(2). Master or Slave mode
can be programmed.
3. This timing parameter is defined from the non-active edge of SCLKN1(2). The active edge of
SCLKN1(2) is the point at which the data is valid.
4. This timing parameter is defined from the active edge of SCLKN1(2). The active edge of SCLKN1(2) is
the point at which the data is valid.
5. Slave mode is defined as SCLKN1(2) and LRCLKN1(2) being driven by an external source.
16
DS339PP4

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