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CS493122-CL Datasheet

  • CS493122-CL

  • Cirrus Logic [Multi-Standard Audio Decoder Family]

  • 1340.73KB

  • CIRRUS

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CS49300 Family DSP
1.10.
Switching Characteristics 鈥?I
2
C
廬
Control Port
(T
A
= 25
擄C;
VA, VD[3:1] = 2.5 V
鹵5%;
Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 20 pF)
Parameter
SCCLK clock frequency
Bus free time between transmissions
Start-condition hold time (prior to first clock pulse)
Clock low time
Clock high time
SCDIO setup time to SCCLK rising
SCDIO hold time from SCCLK falling
Rise time of SCCLK
Fall time of SCCLK
Time from SCCLK falling to CS493XX ACK
Time from SCCLK falling to SCDIO valid during read operation
Time from SCCLK rising to INTREQ rising
Hold time for INTREQ from SCCLK rising
Rise time for INTREQ
Setup time for stop condition
(Note 4)
(Note 5)
(Note 6)
(Note 2)
(Note 3), (Note 7)
(Note 7)
(Note 1)
Symbol
f
scl
t
buf
t
hdst
t
low
t
high
t
sud
t
hdd
t
r
t
f
t
sca
t
scsdv
t
scrh
t
scrl
t
rr
t
susp
4.7
0
**
4.7
4.0
1.2
1.0
250
0
50
300
40
40
200
Min
Max
400
Units
kHz
碌s
碌s
碌s
碌s
ns
碌s
ns
ns
ns
ns
ns
ns
ns
碌s
Notes:. 1. The specification f
scl
indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the software. The
relevant application code user鈥檚 manual should be consulted for the software speed limitations.
2. Data must be held for sufficient time to bridge the 300-ns transition time of SCCLK. This hold time is by
design and not tested.
3. This rise time is
shorter
than that recommended by the I
2
C specifications. For more information, see
Section 6.1, 鈥淪erial Communication鈥?on page 33.
4. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the
last data bit of the last byte of data during a read operation as shown.
5. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next
rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat
this condition as a new read transaction. Send a new start condition followed by the 7-bit address and
the R/W bit (set to 1 for a read). This time is by design and is not tested.
6. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull
up value will affect the rise time.
7. This time is by design and not tested.
14
DS339PP4

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