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CS493122-CL Datasheet

  • CS493122-CL

  • Cirrus Logic [Multi-Standard Audio Decoder Family]

  • 1340.73KB

  • CIRRUS

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CS49300 Family DSP
1.9. Switching Characteristics 鈥?SPI Control Port
(T
A
= 25
擄C;
VA, VD[3:1] = 2.5 V
鹵5%;
Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 20 pF)
Parameter
SCCLK clock frequency
CS falling to SCCLK rising
Rise time of SCCLK line
Fall time of SCCLK lines
SCCLK low time
SCCLK high time
Setup time SCDIN to SCCLK rising
Hold time SCCLK rising to SCDIN
Transition time from SCCLK to SCDOUT valid
Time from SCCLK rising to INTREQ rising
Rise time for INTREQ
Hold time for INTREQ from SCCLK rising
Time from SCCLK falling to CS rising
High time between active CS
Time from CS rising to SCDOUT high-Z
(Note 7)
(Note 2)
(Note 3)
(Note 4)
(Note 4)
(Note 5, 7)
(Note 7)
(Note 7)
(Note 1)
Symbol
f
sck
t
css
t
r
t
f
t
scl
t
sch
t
cdisu
t
cdih
t
scdov
t
scrh
t
rr
t
scrl
t
sccsh
t
csht
t
cscdo
Min
-
20
-
-
150
150
50
50
-
-
-
0
20
200
Max
2000
-
50
50
-
-
-
-
40
200
(Note 6)
-
-
-
20
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 1. The specification f
sck
indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the software. The
relevant application code user鈥檚 manual should be consulted for the software speed limitations.
2. Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK.
3. SCDOUT should
not
be sampled during this time period.
4. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the
second-to-last bit of the last byte of data during a read operation as shown.
5. If INTREQ goes high as indicated in (Note 4), then INTREQ is guaranteed to remain high until the next
rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat
this condition as a new read transaction. Raise chip select to end the current read transaction and then
drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start a new read transaction.
6. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull
up value will affect the rise time.
7. This time is by design and not tested.
12
DS339PP4

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CS493292-CL,CS493302-CL

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