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CS4922 Datasheet

  • CS4922

  • Cirrus Logic [MPEG/G.729A AUDIO DECODER SYSTEM]

  • CIRRUS

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CS4922
If the CS4922 fails to ACK it is possible that the
byte was rejected and it should be transmitted
again. If the second attempt fails the CS4922
should be issued a hardware reset to reinitialize the
communication path.
If the DSP core of the CS4922 wants to send a byte
to the master, it first writes the byte to the Serial
Control Port Output (SCPOUT) register. A write to
the SCPOUT sets the request pin (REQ) active low.
The master must recognize the request and issue a
read operation to the DSP. Figure 14 shows the rel-
ative timing of a single byte read. The master must
Start
SDA
SCL/SCK
AD6
AD5
AD4
AD3
AD2
send the 7 bit address (if address checking is en-
abled it must match the address in the SCPCN reg-
ister) and the read bit. For I
2
C protocol, it is always
the device receiving the transfer that must ACK.
Therefore, the CS4922 will ACK the address and
the read bit. After the ACK by the CS4922 (the fall-
ing edge of SCL/SCK), the serial shift register is
loaded with the byte to be sent and the most signif-
icant bit is placed on the SDA line.
The 8 bit value in the serial shift register is shifted
out by the master. The data is valid on the rising
edge of SCL/SCK and transitions immediately fol-
AD1
AD0
R/W
ACK
Stop
SDA
D7
D6
D5
D4
D3
D2
D1
D0
ACK
SCL/SCK
Figure 12. Control Port Timing, I
2
C
廬
Write
SCK/SCL
M0
SREG
OUTPUT
CONTROL
CDIN
SDA/
CDOUT
CS
REQ
8
8
STATE
MACHINE
INTERRUPT
CONTROL
SCPIN
SCPOUT
SCPCN
INT
8
8
24
24
I/O DATA
BUS
Figure 13. Serial Control Port
19

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