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CS4922 Datasheet

  • CS4922

  • Cirrus Logic [MPEG/G.729A AUDIO DECODER SYSTEM]

  • 643.03KB

  • CIRRUS

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CS4922
AUXLR
AUXCLK
AUXIN
MSB
LSB
MSB
LSB
Left
Right
I
2
S
Input
Figure 9. Auxiliary Data Input Formats
AUXLR
I
2
S Output
AUXCLK
AUXOUT
MSB
LSB
MSB
LSB
Left
Right
Figure 10. Auxiliary Data Output Formats
4.4 Digital Audio Transmitter
The transmitter encodes digital audio data accord-
ing to the Sony
廬
/Philips
廬
Digital Interface Format
(S/PDIF) or the AES/EBU interface format. The
encoded data is output on the TX pin. More infor-
mation on the S/PDIF and AES/EBU standards are
available from Crystal鈥檚 application note library.
4.5 Audio Serial Input Port
The audio serial input port has a three pin interface
consisting of FSYNC, SCLK, and SDATA.
FSYNC is only used to frame data when the audio
data is in a PCM format. Systems, such as MPEG
decoders, which use the audio serial input port for
compressed audio data should tie FSYNC to +5V.
SCLK used to clock SDATA (serial data input) into
an internal FIFO. The active edge of SCLK is de-
termined by the application code running on the
CS4922. Consult the documentation for each ap-
plication download to determine your system re-
quirements.
The port has the capability to support two digital
audio formats. The formats are illustrated in Fig-
ures 9, 10, and 11. The input and output formats
are always configured to operate in the same mode.
The input and output sampling rates are the same as
the sample rate for the on-chip DAC. The AUX
port can support 18 bit samples at 64Fs (I
2
S For-
mat) or 20 bit samples at 128Fs (Left Justified For-
mat).
The CS4922 Auxiliary digital audio port physically
is implemented with four device pins: AUXCLK
pin 11, AUXLR pin 10, AUXIN pin 9, and AUX-
OUT pin 8. AUXCLK is utilized as the primary
synchronous clock. AUXOUT is the serial audio
data output pin and AUXIN is the serial audio data
input pin. AUXLR is an output pin used for fram-
ing the auxiliary digital audio port. AUXLR cycles
at the same Fs as the on-chip stereo DAC. Fs is
programmed by the DSP. AUXLR and AUXOUT
transition with the falling edge of AUXCLK. The
rising edge of AUXCLK samples AUXIN.
4.6 Auxiliary Digital Audio Port
The CS4922 auxiliary port provides a path for the
internal DSP core to directly read and write framed
PCM digital audio data. The auxiliary port is de-
signed to operate in a full duplex mode that can
support simultaneous PCM input and output. It is
important to note that the CS4922 always masters
the audio clocks on the Auxiliary Digital Audio
Port.
4.7 Serial Control Port
The serial control port (SCP) can operate in I
2
C or
SPI compatible modes. In either mode, the control
port performs eight bit transfers and is always con-
figured as a slave. As a slave, it cannot drive the
clock signal nor initiate data transfers. The port can
request to be serviced by activating the REQ pin.
The port is an asynchronous interface which pro-
vides interrupts and handshaking signals to allow
17

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