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BQ4010_07 Datasheet

  • BQ4010_07

  • Texas Instruments [8 k x 8 NONVOLATILE SRAM (5 V, 3.3 V)]

  • TI

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bq4010/Y/LY
www.ti.com
SLUS116A 鈥?MAY 1999 鈥?REVISED APRIL 2007
Table 5. 3.3-V POWER-DOWN/POWER-UP (T
A
= T
OPR
)
PARAMETER
t
F
t
R
t
CER
t
DR
(1)
(2)
V
CC
slew, 3 V to 0 V
V
CC
slew, V
SO
to V
PFD (max)
Chip enable recovery time
Data-retention time in absence of V
CC
Time during which SRAM is write-protected after
V
CC
passes V
PFD
on power-up.
T
A
= 25擄C
(2)
TEST CONDITIONS
MIN TYP
(1)
300
100
10
10
85
MAX
UNIT
碌s
ms
years
Typical values indicate operation at T
A
= 25擄C, V
CC
= 3.3 V.
Batteries are disconnected from circuit until after V
CC
is applied for the first time. Data retention time (t
DR
) is the accumulated time in
absence of power beginning when power is first applied to the device.
V
CC
3.0 V
V
PFD
V
SO
V
SO
V
PFD(max)
t
R
t
DR
t
F
t
CER
CE
Figure 11. 3.3-V Power-Down/Power-Up Timing
CAUTION:
Negative undershoots below the absolute maximum rating of -0.3 V in
battery-backup mode may affect data integrity.
14
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