P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Sector Erase Time
Chip Erase Time (Note 3)
Byte Programming Time (Note 5)
Word Programming Time (Note 5)
Chip Programming Time (Notes 3, 5)
Erase/Program Endurance
Typ (Note 1)
1.0
19
7
14
7.2
1,000,000
Max (Note 2)
8
152
300
600
21.6
Unit
sec
sec
碌s
碌s
sec
cycles
Minimum 100,000 cycles guaranteed
Comments
Excludes 00H programming prior to
erasure
Excludes system-level overhead (Note 4)
Notes:
1. The typical erase and programming times assume the following conditions: 25
擄
C, 5.0 volt V
CC
, 100,000 cycles. These
conditions do not apply to erase/program endurance. Programming typicals assume checkerboard pattern.
2. The maximum erase and programming times assume the following conditions: 90
擄
C, 4.5 volt V
CC
, 100,000 cycles.
3. Although Embedded Algorithms allow for longer chip program and erase time, the actual time will be considerably less since
bytes program or erase significantly faster than the worst case byte.
4. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each
byte. In the preprogramming step of the Embedded Erase algorithm, all bytes are programmed to 00H before erasure.
5. The Embedded Algorithms allow for 2.5 ms byte program time. DQ5 = 鈥?鈥?only after a byte takes the theoretical maximum
time to program. A minimal number of bytes may require significantly more programming pulses than the typical byte. The
majority of the bytes will program within one or two pulses. This is demonstrated by the Typical and Maximum Programming
Times listed above.
LATCHUP CHARACTERISTICS
Min
Input Voltage with respect to V
SS
on all I/O pins
V
CC
Current
鈥?.0 V
鈥?00 mA
Max
V
CC
+ 1.0 V
+100 mA
Includes all pins except V
CC
. Test conditions: V
CC
= 5.0 V, one pin at a time.
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Am29F800T/Am29F800B
8/18/97