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AM29F800B-120 Datasheet

  • AM29F800B-120

  • Advanced Micro Devices [8 Megabit (1,048,576 x 8-Bit/524,28...

  • AMD

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P R E L I M I N A R Y
Read/Reset Command
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for
reads until the command register contents are altered.
The device will automatically power-up in the read/
reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read
cycles will retrieve array data. This default value en-
sures that no spurious alteration of the memory content
occurs during the power transition. Refer to the AC
Read Characteristics and Waveforms for the specific
timing parameters.
the system is
not
required to provide further controls or
timings. The device will automatically provide adequate
internally generated program pulses and verify the pro-
grammed cell margin.
The automatic programming operation is completed
when the data on DQ7 (also used as Data Polling) is
equivalent to the data written to this bit at which time
the device returns to the read mode and addresses are
no longer latched (see Table 8, Hardware Sequence
Flags). Therefore, the device requires that a valid ad-
dress to the device be supplied by the system at this
particular instance of time for Data Polling operations.
Data Polling must be performed at the memory location
which is being programmed.
Any commands written to the chip during the Embed-
ded Program Algorithm will be ignored. If a hardware
reset occurs during the programming operation, the
data at that particular location will be corrupted.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data 鈥?鈥?cannot be
programmed back to a 鈥?鈥? Attempting to do so may
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success, according
to the data polling algorithm, but a read from reset/read
mode will show that the data is still 鈥?鈥? Only erase op-
erations can convert 鈥?鈥漵 to 鈥?鈥漵.
Figure 1 illustrates the Embedded Programming Algo-
rithm using typical command strings and
bus operations.
Autoselect Command
Flash memories are intended for use in applications
where the local CPU can alter memory contents. As
such, manufacture and device codes must be accessi-
ble while the device resides in the target system.
PROM programmers typically access the signature
codes by raising A9 to a high voltage. However, multi-
plexing high voltage onto the address lines is not gen-
erally a desirable system design practice.
The device contains an autoselect command operation
to supplement traditional PROM programming method-
ology. The operation is initiated by writing the autose-
lect command sequence into the command register.
Following the command write, a read cycle from ad-
dress XX00H retrieves the manufacture code of 01H. A
read cycle from address XX01H returns the device
code (Am29F800T = D6H and Am29F800B = 58H for
x8 mode; Am29F800T = 22D6H and Am29F800B =
2258H for x16 mode) (see Tables 3 and 4).
All manufacturer and device codes will exhibit odd par-
ity with DQ7 defined as the parity bit.
Furthermore, the write protect status of sectors can be
read in this mode. Scanning the sector addresses
(A18, A17, A16, A15, A14, A13, and A12) while (A6,
A1, A0) = (0, 1, 0) will produce a logical 鈥?鈥?at device
output DQ0 for a protected sector.
To terminate the operation, it is necessary to write the
read/reset command sequence into the register.
Chip Erase
Chip erase is a six bus cycle operation. There are two
鈥渦nlock鈥?write cycles. These are followed by writing the
鈥渟et-up鈥?command. Two more 鈥渦nlock鈥?write cycles are
then followed by the chip erase command.
Chip erase does
not
require the user to program the
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device will
automatically program and verify the entire memory for
an all zero data pattern prior to electrical erase. The
erase is performed sequentially on all sectors at the
same time (see Table 鈥淓rase and Programming Perfor-
mance鈥?. The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and termi-
nates when the data on DQ7 is 鈥?鈥?(see Write Opera-
tion Status section) at which time the device returns to
read the mode.
Figure 2 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Byte/Word Programming
The device is programmed on a byte-by-byte (or
word-by-word) basis. Programming is a four bus cycle
operation. There are two 鈥渦nlock鈥?write cycles. These
are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge
of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever hap-
pens first. The rising edge of CE or WE (whichever
happens first) begins programming using the Embed-
ded Program Algorithm. Upon executing the algorithm,
14
Am29F800T/Am29F800B
8/18/97

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