P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase Time
Chip Erase Time
Byte Programming Time
Chip Programming Time (Note 3)
Typ (Note 1)
1
32
7
14.4
Max (Note 2)
8
256
300
43.2
Unit
sec
sec
碌s
sec
Comments
Excludes 00h programming prior to
erasure (Note 4)
Excludes system-level overhead
(Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25
擄
C, 5.0 V V
CC
, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90擄C, V
CC
= 4.5 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 6 for further
information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Min
Input Voltage with respect to V
SS
on I/O pins
V
CC
Current
鈥?.0 V
鈥?00 mA
Max
V
CC
+ 1.0 V
+100 mA
Includes all pins except V
CC
. Test conditions: V
CC
= 5.0 Volt, one pin at a time.
TSOP PIN CAPACITANCE
Parameter
Symbol
C
IN
C
OUT
C
IN2
Parameter Description
Input Capacitance
Output Capacitance
Control Pin Capacitance
V
IN
= 0
V
OUT
= 0
V
IN
= 0
Test Conditions
Min
6
8.5
7.5
Max
7.5
12
9
Unit
pF
pF
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25
擄
C, f = 1.0 MHz.
DATA RETENTION
Parameter
Minimum Pattern Data Retention Time
125擄C
20
Years
Test Conditions
150擄C
Min
10
Unit
Years
Am29F017B
33