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AD7846AP Datasheet

  • AD7846AP

  • 16-Bit Voltage Output DAC

  • 617.26KB

  • AD

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AD7846
V
REF+
SEGMENT 16
R
DAC1
S1
S3
S2
S4
DAC2
R
IN
R
DAC3
A1
12 BIT DAC
A3
V
OUT
S15
S17
S14
S16
A2
DB11鈥揇B0
DB15鈥揇B12
DB15鈥揇B12
SEGMENT 1
V
REF鈥?/div>
Figure 16. D/A Conversion
Output Stage
+15V
+5V
The output stage of the AD7846 is shown in Figure 17. It is
capable of driving a 2 k鈩?1000 pF load. It also has a resistor
feedback network which allows the user to configure it for gains
of one or two. Table I shows the different output ranges that are
possible.
An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately 2.5
碌s
after the leading edge of
LDAC.
This short state keeps the DAC
output at its previous voltage while the AD7846 is internally
changing to its new value. So, any glitches that occur in the
transition are not seen at the output. In systems where the
LDAC
is tied permanently low, the deglitching will not be in
operation. Figures 8 and 9 show the outputs of the AD7846
without and with the deglitcher.
R
IN
10k
C1
1 F
4
V
DD
V
REF+
R1
10k
V
CC
V
OUT
V
OUT
(0V TO +10V)
AD586
AD7846*
V
REF鈥?/div>
V
SS
R
IN
DGND
SIGNAL
GROUND
*ADDITIONAL PINS
OMITTED FOR CLARITY
鈥?5V
Figure 18. Unipolar Binary Operation
Table III. Code Table for Figure 18
10k
C1
Binary Number
in DAC Latch
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
Analog Output
(V
OUT
)
+10 (65535/65536) V
+10 (32768/65536) V
+10 (1/65536) V
0
V
OUT
DAC3
ONE
SHOT
NOTE
1 LSB = 10 V/2
16
= 10 V/65536 = 152
碌V.
LDAC
Figure 17. Output Stage
UNIPOLAR BINARY OPERATION
Figure 18 shows the AD7846 in the unipolar binary circuit
configuration. The DAC is driven by the AD586, +5 V refer-
ence. Since R
IN
is tied to 0 V, the output amplifier has a gain of
2 and the output range is 0 V to +10 V. If a 0 V to +5 V range is
required, R
IN
should be tied to V
OUT
, configuring the output
stage for a gain of 1. Table III gives the code table for the circuit
of Figure 18.
Offset and gain may be adjusted in Figure 18 as follows: To
adjust offset, disconnect the V
REF鈥?/div>
input from 0 V, load the
DAC with all 0s and adjust the V
REF鈥?/div>
voltage until V
OUT
= 0 V.
For gain adjustment, the AD7846 should be loaded with all 1s
and R1 adjusted until V
OUT
= 10 (65535)/(65536) = 9.999847 V.
If a simple resistor divider is used to vary the V
REF鈥?/div>
voltage, it is
important that the temperature coefficients of these resistors
match that of the DAC input resistance (鈥?00 ppm/擄C). Other-
wise, extra offset errors will be introduced over temperature.
Many circuits will not require these offset and gain adjustments.
In these circuits, R1 can be omitted. Pin 5 of the AD586 may be
left open circuit and Pin 8 (V
REF鈥?/div>
) of the AD7846 tied to 0 V.
鈥?鈥?/div>
REV. E

AD7846AP 產(chǎn)品屬性

  • Data Converter FundamentalsDAC Architectures

  • 1

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器

  • -

  • 7µs

  • 16

  • 并聯(lián)

  • 1

  • 雙 ±

  • 100mW

  • -40°C ~ 85°C

  • 表面貼裝

  • 28-LCC（J 形引線(xiàn)）

  • 28-PLCC（11.51x11.51）

  • 管件

  • 1 電壓，單極；1 電壓，雙極

  • 143k

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