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AD7846AP Datasheet

  • AD7846AP

  • 16-Bit Voltage Output DAC

  • AD

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AD7846
A1鈥揂23
ADDRESS BUS
ANALOG SUPPLY
+15V
0V
鈥?5V
CS
+5V
CLR
LDAC
DIGITAL SUPPLY
+5V DGND
MC68000
DS
DTACK
ADDRESS
DECODE
AD7846*
R/W
D0鈥揇15
DATA BUS
*LINEAR CIRCUITRY
OMITTED FOR CLARITY
R/W
DB0鈥揇B15
R1
SIGNAL
GROUND
R2
Figure 25. AD7846-to-MC68000 Interface
DIGITAL FEEDTHROUGH
AD588*
R3
AD7846*
R4
R
L
V
OUT
(+5V TO 鈥?V)
In the preceding interface configurations, most digital inputs to
the AD7846 are directly connected to the microprocessor bus.
Even when the device is not selected, these inputs will be con-
stantly changing. The high frequency logic activity on the bus
can feed through the DAC package capacitance to show up as
noise on the analog output. To minimize this Digital Feed-
through isolate the DAC from the noise source. Figure 26 shows
an interface circuit which isolates the DAC from the bus.
R5
*ADDITIONAL PINS
OMITTED FOR CLARITY
Figure 27. AD7846 Grounding
A1鈥揂15
ADDRESS BUS
ADDRESS
DECODE
MICRO-
PROCESSOR
+5V
CS
CLR
LDAC
R1 to R5 represent lead and track resistances on the printed
circuit board. R1 is the resistance between the Analog Power
Supply ground and the Signal Ground. Since current flowing in
R1 is very low (bias current of AD588 sense amplifier), the
effect of R1 is negligible. R2 and R3 represent track resistance
between the AD588 outputs and the AD7846 reference inputs.
Because of the Force and Sense outputs on the AD588, these
resistances will also have a negligible effect on accuracy.
R4 is the resistance between the DAC output and the load. If
R
L
is constant, then R4 will introduce a gain error only which
can be trimmed out in the calibration cycle. R5 is the resistance
between the load and the analog common. If the output voltage
is sensed across the load, R5 will introduce a further gain error
which can be trimmed out. If, on the other hand, the output
voltage is sensed at the analog supply common, R5 appears as
part of the load and therefore introduces no errors.
Printed Circuit Board Layout
R/W
DIR
DATA BUS
B BUS
G
A BUS
R/W
AD7846*
DB0鈥揇B15
D0鈥揇15
2
74LS245
*LINEAR CIRCUITRY
OMITTED FOR CLARITY
Figure 26. AD7846 Interface Circuit Using Latches to Mini-
mize Digital Feedthrough
Note that to make use of the AD7846 readback feature using
the isolation technique of Figure 26, the latch needs to be
bidirectional.
APPLICATION HINTS
Noise
Figure 28 shows the AD7846 in a typical application with the
AD588 reference, producing an output analog voltage in the
鹵
10 volts range. Full scale and bipolar zero adjustment are
provided by potentiometers R2 and R3. Latches (2
脳
74LS245)
isolate the DAC digital inputs from the active microprocessor
bus and minimize digital feedthrough.
The printed circuit board layout for Figure 28 is shown in Fig-
ures 29 and 30. Figure 29 is the component side layout while
Figure 30 is the solder side layout. The component overlay is
shown in Figure 31.
In the layout, the general grounding guidelines given in Figure
27 are followed. The AD588 and AD7846 are as close as pos-
sible, and the decoupling capacitors for these are also kept as
close to the device pins as possible.
In high resolution systems, noise is often the limiting factor.
With a 10 volt span, a 16-bit LSB is 152
碌V
(鈥?6 dB). Thus, the
noise floor must stay below 鈥?6 dB in the frequency range of
interest. Figure 7 shows the noise spectral density for the AD7846.
Grounding
As well as noise, the other prime consideration in high resolu-
tion DAC systems is grounding. With an LSB size of 152
碌V
and a load current of 5 mA, 1 LSB of error can be introduced
by series resistance of only 0.03
鈩?
Figure 27 below shows recommended grounding for the AD7846
in a typical application.
鈥?2鈥?/div>
REV. E

AD7846AP 產(chǎn)品屬性

  • Data Converter FundamentalsDAC Architectures

  • 1

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器

  • -

  • 7µs

  • 16

  • 并聯(lián)

  • 1

  • 雙 ±

  • 100mW

  • -40°C ~ 85°C

  • 表面貼裝

  • 28-LCC（J 形引線）

  • 28-PLCC（11.51x11.51）

  • 管件

  • 1 電壓，單極；1 電壓，雙極

  • 143k

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