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PIC18F8620 Datasheet

  • PIC18F8620

  • 64/80-Pin High-Performance,256 Kbit to 1 Mbit Enhanced Flash...

  • 3273.72KB

  • 380頁

  • Microchip   Microchip

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PIC18F6520/8520/6620/8620/6720/8720
REGISTER 9-2:
INTCON2 REGISTER
R/W-1
RBPU
bit 7
bit 7
RBPU:
PORTB Pull-up Enable bit
1
= All PORTB pull-ups are disabled
0
= PORTB pull-ups are enabled by individual port latch values
INTEDG0:
External Interrupt 0 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
INTEDG1:
External Interrupt 1 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
INTEDG2:
External Interrupt 2 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
INTEDG3:
External Interrupt 3 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
TMR0IP:
TMR0 Overflow Interrupt Priority bit
1
= High priority
0
= Low priority
INT3IP:
INT3 External Interrupt Priority bit
1
= High priority
0
= Low priority
RBIP:
RB Port Change Interrupt Priority bit
1
= High priority
0
= Low priority
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
鈥?鈥?= Bit is cleared
x = Bit is unknown
R/W-1
INTEDG0
R/W-1
INTEDG1
R/W-1
INTEDG2
R/W-1
INTEDG3
R/W-1
TMR0IP
R/W-1
INT3IP
R/W-1
RBIP
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
DS39609B-page 90
錚?/div>
2004 Microchip Technology Inc.

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