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PIC18F8620 Datasheet

  • PIC18F8620

  • 64/80-Pin High-Performance,256 Kbit to 1 Mbit Enhanced Flash...

  • 380頁

  • Microchip   Microchip

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PIC18F6520/8520/6620/8620/6720/8720
5.5
Writing to Flash Program Memory
The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding reg-
isters needed to program the Flash memory. There are
8 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the
TBLWT
instruction has to be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes, because only
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
FIGURE 5-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
TBLPTR =
xxxxx0
TBLPTR =
xxxxx1
8
TBLPTR =
xxxxx2
8
TBLPTR =
xxxxx7
8
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
5.5.1
FLASH PROGRAM MEMORY
WRITE SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer with address being erased.
Do the row erase procedure.
Load Table Pointer with address of first byte
being written.
Write the first 8 bytes into the holding registers
with auto-increment.
Set the EECON1 register for the write operation:
鈥?set EEPGD bit to point to program memory
鈥?clear the CFGS bit to access program
memory
鈥?set WREN to enable byte writes
Disable interrupts.
9.
10.
11.
12.
13.
14.
15.
16.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write (about
2 ms using internal timer).
Execute a
NOP.
Re-enable interrupts.
Repeat steps 6-14 seven times, to write
64 bytes.
Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 5-3.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the eight bytes
in the holding register.
8.
錚?/div>
2004 Microchip Technology Inc.
DS39609B-page 67

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