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PIC18F8620 Datasheet

  • PIC18F8620

  • 64/80-Pin High-Performance,256 Kbit to 1 Mbit Enhanced Flash...

  • 380頁(yè)

  • Microchip   Microchip

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PIC18F6520/8520/6620/8620/6720/8720
3.1
Power-on Reset (POR)
3.3
Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when
V
DD
rise is detected. To take advantage of the POR
circuitry, tie the MCLR pin through a 1 k鈩?to 10 k鈩?/div>
resistor to V
DD
. This will eliminate external RC
components usually needed to create a Power-on
Reset delay. A minimum rise rate for V
DD
is specified
(parameter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
Sleep.
3.4
PLL Lock Time-out
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD
POWER-UP)
V
DD
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to
provide a fixed time-out that is sufficient for the PLL to
lock to the main oscillator frequency. This PLL lock
time-out (T
PLL
) is typically 2 ms and follows the
oscillator start-up time-out.
3.5
R1
MCLR
C
Brown-out Reset (BOR)
D
R
PIC18FXX20
Note 1:
External Power-on Reset circuit is required
only if the V
DD
power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when V
DD
powers down.
R < 40 k鈩?is recommended to make sure that
the voltage drop across R does not violate
the device鈥檚 electrical specification.
R1 = 1 k鈩?to 10 k鈩?will limit any current flow-
ing into MCLR from external capacitor C, in
the event of MCLR/V
PP
pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
2:
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If V
DD
falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A Reset may not occur if V
DD
falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until V
DD
rises above
BV
DD
. If the Power-up Timer is enabled, it will be
invoked after V
DD
rises above BV
DD
; it then will keep
the chip in Reset for an additional time delay (parame-
ter #33). If V
DD
drops below BV
DD
while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
V
DD
rises above BV
DD
, the Power-up Timer will
execute the additional time delay.
3:
3.6
Time-out Sequence
3.2
Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Reset as long as the PWRT is active.
The PWRT鈥檚 time delay allows V
DD
to rise to an accept-
able level. A configuration bit is provided to enable/
disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to V
DD
, temperature and process variation. See DC
parameter #33 for details.
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figures 3-3 through 3-7 depict time-out sequences on
power-up.
Since the time-outs occur from the POR pulse, the
time-outs will expire if MCLR is kept low long enough.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXX20 device
operating in parallel.
Table 3-2 shows the Reset conditions for some Special
Function Registers, while Table 3-3 shows the Reset
conditions for all of the registers.
DS39609B-page 30
錚?/div>
2004 Microchip Technology Inc.

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