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PIC18F8620 Datasheet

  • PIC18F8620

  • 64/80-Pin High-Performance,256 Kbit to 1 Mbit Enhanced Flash...

  • 380頁

  • Microchip   Microchip

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PIC18F6520/8520/6620/8620/6720/8720
3.0
RESET
differentiate
between
The PIC18FXX20 devices
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 3-2.
These bits are used in software to determine the nature
of the Reset. See Table 3-3 for a full description of the
Reset states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses. The MCLR pin is not driven low by
any internal Resets, including the WDT.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (PBOR)
RESET
Instruction
Stack Full Reset
Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a 鈥淩eset
state鈥?on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during Sleep and by the
RESET
instruction.
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLR
WDT
Module
WDT
Time-out
Reset
Sleep
V
DD
Rise Power-on Reset
Detect
V
DD
Brown-out
Reset
BOREN
OST/PWRT
OST
10-bit Ripple Counter
OSC1
PWRT
On-chip
RC OSC
(1)
10-bit Ripple Counter
R
Q
Chip_Reset
S
Enable PWRT
Enable OST
(2)
Note 1:
2:
This is a separate oscillator from the RC oscillator of the CLKI pin.
See Table 3-1 for time-out situations.
錚?/div>
2004 Microchip Technology Inc.
DS39609B-page 29

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