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PIC18F8620 Datasheet

  • PIC18F8620

  • 64/80-Pin High-Performance,256 Kbit to 1 Mbit Enhanced Flash...

  • 380頁

  • Microchip   Microchip

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PIC18F6520/8520/6620/8620/6720/8720
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority Registers (IPR1, IPR2 and IPR3). The
operation of the priority bits requires that the Interrupt
Priority Enable (IPEN) bit be set.
REGISTER 9-10:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP
(1)
bit 7
R/W-1
ADIP
R/W-1
RC1IP
R/W-1
TX1IP
R/W-1
SSPIP
R/W-1
CCP1IP
R/W-1
TMR2IP
R/W-1
TMR1IP
bit 0
bit 7
PSPIP:
Parallel Slave Port Read/Write Interrupt Priority bit
(1)
1
= High priority
0
= Low priority
ADIP:
A/D Converter Interrupt Priority bit
1
= High priority
0
= Low priority
RC1IP:
USART1 Receive Interrupt Priority bit
1
= High priority
0
= Low priority
TX1IP:
USART1 Transmit Interrupt Priority bit
1
= High priority
0
= Low priority
SSPIP:
Master Synchronous Serial Port Interrupt Priority bit
1
= High priority
0
= Low priority
CCP1IP:
CCP1 Interrupt Priority bit
1
= High priority
0
= Low priority
TMR2IP:
TMR2 to PR2 Match Interrupt Priority bit
1
= High priority
0
= Low priority
TMR1IP:
TMR1 Overflow Interrupt Priority bit
1
= High priority
0
= Low priority
Note 1:
Enabled only in Microcontroller mode for PIC18F8X20 devices.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
鈥?鈥?= Bit is cleared
x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39609B-page 98
錚?/div>
2004 Microchip Technology Inc.

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