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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 2082.75KB

  • 270頁

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
7.2
Clock Switching Operation
1.
The clock switching hardware compares the
COSC status bits with the new value of the
NOSC control bits. If they are the same, the
clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
If a valid clock switch has been initiated, the
LOCK
(OSCCON<5>)
and
the
CF
(OSCCON<3>) status bits are cleared.
The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK =
1).
The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or LP (if LPOSCEN remains set).
Note 1:
The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
2:
Direct clock switches between any primary
oscillator mode with PLL and FRCPLL
mode are not permitted. This applies to
clock switches in either direction. In these
instances, the application must switch to
FRC mode as a transition clock source
between the two PLL modes.
Applications are free to switch among any of the four
clock sources (Primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, dsPIC33FJ32GP202/204 and
dsPIC33FJ16GP304 devices have a safeguard lock
built into the switch process.
Note:
Primary Oscillator mode has three different
submodes (XT, HS and EC), which are
determined by the POSCMD<1:0> Config-
uration bits. While an application can
switch to and from Primary Oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
2.
3.
4.
7.2.1
ENABLING CLOCK SWITCHING
5.
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register must be programmed to
鈥?鈥? (Refer to
Section 18.1 鈥淐onfiguration Bits鈥?/span>
for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (鈥?鈥?, the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
The NOSC control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSC bits (OSCCON<14:12>)
reflect the clock source selected by the FNOSC
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at 鈥?鈥?at all
times.
6.
7.2.2
Performing
sequence:
1.
OSCILLATOR SWITCHING
SEQUENCE
a
clock
switch requires this
basic
7.3
Fail-Safe Clock Monitor (FSCM)
2.
3.
4.
5.
If
desired,
read
the
COSC
bits
(OSCCON<14:12>) to determine the current
oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register high byte.
Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
Perform the unlock sequence to allow a write to
the OSCCON register low byte.
Set the OSWEN bit to initiate the oscillator
switch.
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
漏
2007 Microchip Technology Inc.
Preliminary
DS70290A-page 97

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