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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 2082.75KB

  • 270頁

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
REGISTER 7-2:
R/W-0
ROI
bit 15
R/W-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
y = Value set from Configuration bits on POR
W = Writable bit
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
鈥?鈥?= Bit is cleared
x = Bit is unknown
R/W-1
U-0
鈥?/div>
R/W-0
R/W-0
R/W-0
PLLPRE<4:0>
bit 0
R/W-0
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
R/W-0
DOZE<2:0>
R/W-0
R/W-0
DOZEN
(1)
R/W-1
R/W-0
FRCDIV<2:0>
R/W-0
bit 8
R/W-0
PLLPOST<1:0>
ROI:
Recover on Interrupt bit
1
= Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0
= Interrupts have no effect on the DOZEN bit
DOZE<2:0>:
Processor Clock Reduction Select bits
000
= F
CY
/1
001
= F
CY
/2
010
= F
CY
/4
011
= F
CY
/8 (default)
100
= F
CY
/16
101
= F
CY
/32
110
= F
CY
/64
111
= F
CY
/128
DOZEN:
DOZE Mode Enable bit
(1)
1
= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0
= Processor clock/peripheral clock ratio forced to 1:1
FRCDIV<2:0>:
Internal Fast RC Oscillator Postscaler bits
000
= FRC divide by 1 (default)
001
= FRC divide by 2
010
= FRC divide by 4
011
= FRC divide by 8
100
= FRC divide by 16
101
= FRC divide by 32
110
= FRC divide by 64
111
= FRC divide by 256
PLLPOST<1:0>:
PLL VCO Output Divider Select bits (also denoted as 鈥楴2鈥? PLL postscaler)
00
= Output/2
01
= Output/4 (default)
10
= Reserved
11
= Output/8
Unimplemented:
Read as 鈥?鈥?/div>
PLLPRE<4:0>:
PLL Phase Detector Input Divider bits (also denoted as 鈥楴1鈥? PLL prescaler)
00000
= Input/2 (default)
00001
= Input/3
鈥⑩€⑩€?/div>
11111
= Input/33
This bit is cleared when the ROI bit is set and an interrupt occurs.
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5
bit 4-0
Note 1:
DS70290A-page 94
Preliminary
漏
2007 Microchip Technology Inc.

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