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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 270頁

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
EQUATION 7-2:
F
OSC
CALCULATION
M
(
N1*N2
)
鈥?If PLLPOST<1:0> =
0,
then N2 = 2. This provides
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
F
OSC
= F
IN
*
For example, suppose a 10 MHz crystal is being used,
with 鈥淴T with PLL鈥?being the selected oscillator mode.
鈥?If PLLPRE<4:0> =
0,
then N1 = 2. This yields a
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
鈥?If PLLDIV<8:0> = 0x1E, then M = 32. This yields a
VCO output of 5 x 32 = 160 MHz, which is within
the 100-200 MHz ranged needed.
EQUATION 7-3:
XT WITH PLL MODE
EXAMPLE
F
CY
=
F
OSC
1 10000000*32
=
= 40 MIPS
2
2
2*2
(
)
FIGURE 7-2:
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 PLL BLOCK DIAGRAM
0.8-8.0 MHz
Here
100-200 MHz
Here
12.5-80 MHz
Here
F
OSC
Source (Crystal, External Clock
or Internal RC)
PLLPRE
X
VCO
PLLDIV
PLLPOST
Divide by
2-33
Divide by
2-513
Divide by
2, 4, 8
TABLE 7-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Source
Internal
Internal
Internal
Secondary
Primary
Primary
Primary
Primary
Primary
Primary
Internal
Internal
POSCMD<1:0>
xx
xx
xx
xx
10
01
00
10
01
00
xx
xx
FNOSC<2:0>
111
110
101
100
011
011
011
010
010
010
001
000
1
1
1
1
Note
1, 2
1
1
1
Oscillator Mode
Fast RC Oscillator with Divide-by-N
(FRCDIVN)
Fast RC Oscillator with Divide-by-16
(FRCDIV16)
Low-Power RC Oscillator (LPRC)
Secondary (Timer1) Oscillator (SOSC)
Primary Oscillator (HS) with PLL
(HSPLL)
Primary Oscillator (XT) with PLL
(XTPLL)
Primary Oscillator (EC) with PLL
(ECPLL)
Primary Oscillator (HS)
Primary Oscillator (XT)
Primary Oscillator (EC)
Fast RC Oscillator with PLL (FRCPLL)
Fast RC Oscillator (FRC)
Note 1:
2:
OSC2 pin function is determined by the OSCIOFNC Configuration bit.
This is the default oscillator mode for an unprogrammed (erased) device.
漏
2007 Microchip Technology Inc.
Preliminary
DS70290A-page 91

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