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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 270頁

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
7.1
CPU Clocking System
7.1.2
SYSTEM CLOCK SELECTION
The oscillator source used at a device Power-on Reset
event is selected using Configuration bit settings. The
oscillator Configuration bit settings are located in the
Configuration registers in the program memory. (Refer to
Section 18.1 鈥淐onfiguration Bits鈥?/span>
for further details.)
The Initial Oscillator Selection Configuration bits,
FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscil-
lator Mode Select Configuration bits, POSCMD<1:0>
(FOSC<1:0>), select the oscillator source that is used at
a Power-on Reset. The FRC primary oscillator is the
default (unprogrammed) selection.
The Configuration bits allow users to choose among 12
different clock modes, shown in Table 7-1.
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) F
OSC
is divided by 2 to
generate the device instruction clock (F
CY
). F
CY
defines the operating speed of the device, and speeds
up to
40
MHz
are
supported by
the
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
architecture.
Instruction execution speed or device operating
frequency, F
CY
, is given by:
The
dsPIC33FJ32GP202/204
and
dsPIC33FJ16GP304 device provides seven system
clock options:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Fast RC (FRC) Oscillator
FRC Oscillator with PLL
Primary (XT, HS or EC) Oscillator
Primary Oscillator with PLL
Secondary (LP) Oscillator
Low-Power RC (LPRC) Oscillator
FRC Oscillator with postscaler
7.1.1
7.1.1.1
SYSTEM CLOCK SOURCES
Fast RC
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
7.1.1.2
Primary
The primary oscillator can use one of the following as
its clock source:
鈥?XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
鈥?HS (High-Speed Crystal): Crystals in the range of
10 MHz to 40 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
鈥?EC (External Clock): External clock signal in the
range of 0.8 MHz to 64 MHz. The external clock
signal is directly applied to the OSC1 pin.
EQUATION 7-1:
DEVICE OPERATING
FREQUENCY
F
CY
= F
OSC
/2
7.1.3
PLL CONFIGURATION
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 7-2.
The output of the primary oscillator or FRC, denoted as
鈥楩
IN
鈥? is divided down by a prescale factor (N1) of 2, 3,
... or 33 before being provided to the PLL鈥檚 Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale factor 鈥楴1鈥?is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor 鈥楳,鈥?/div>
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor
鈥楴2.鈥?This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). 鈥楴2鈥?can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(F
OSC
) is in the range of 12.5 MHz to 80 MHz, which
generates device operating speeds of 6.25-40 MIPS.
For a primary oscillator or FRC oscillator, output 鈥楩
IN
鈥?
the PLL output 鈥楩
OSC
鈥?is given by:
7.1.1.3
Secondary
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
7.1.1.4
Low-Power RC
The Low-Power RC (LPRC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
7.1.1.5
FRC
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase Locked Loop (PLL) to provide a wide range of
output frequencies for device operation. PLL
configuration is described in
Section 7.1.3 鈥淧LL
Configuration鈥?
DS70290A-page 90
Preliminary
漏
2007 Microchip Technology Inc.

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