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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 270頁

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
REGISTER 6-8:
U-0
鈥?/div>
bit 15
R/W-0
T2IE
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
W = Writable bit
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
鈥?鈥?= Bit is cleared
x = Bit is unknown
R/W-0
OC2IE
R/W-0
IC2IE
U-0
鈥?/div>
R/W-0
T1IE
R/W-0
OC1IE
R/W-0
IC1IE
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
鈥?/div>
R/W-0
AD1IE
R/W-0
U1TXIE
R/W-0
U1RXIE
R/W-0
SPI1IE
R/W-0
SPI1EIE
R/W-0
T3IE
bit 8
R/W-0
INT0IE
bit 0
Unimplemented:
Read as 鈥?鈥?/div>
AD1IE:
ADC1 Conversion Complete Interrupt Enable bit
1
= Interrupt request enabled
0
= Interrupt request not enabled
U1TXIE:
UART1 Transmitter Interrupt Enable bit
1
= Interrupt request enabled
0
= Interrupt request not enabled
U1RXIE:
UART1 Receiver Interrupt Enable bit
1
= Interrupt request enabled
0
= Interrupt request not enabled
SPI1IE:
SPI1 Event Interrupt Enable bit
1
= Interrupt request enabled
0
= Interrupt request not enabled
SPI1EIE:
SPI1 Error Interrupt Enable bit
1
= Interrupt request enabled
0
= Interrupt request not enabled
T3IE:
Timer3 Interrupt Enable bit
1
= Interrupt request enabled
0
= Interrupt request not enabled
T2IE:
Timer2 Interrupt Enable bit
1
= Interrupt request enabled
0
= Interrupt request not enabled
OC2IE:
Output Compare Channel 2 Interrupt Enable bit
1
= Interrupt request enabled
0
= Interrupt request not enabled
IC2IE:
Input Capture Channel 2 Interrupt Enable bit
1
= Interrupt request enabled
0
= Interrupt request not enabled
Unimplemented:
Read as 鈥?鈥?/div>
T1IE:
Timer1 Interrupt Enable bit
1
= Interrupt request enabled
0
= Interrupt request not enabled
OC1IE:
Output Compare Channel 1 Interrupt Enable bit
1
= Interrupt request enabled
0
= Interrupt request not enabled
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
DS70290A-page 74
Preliminary
漏
2007 Microchip Technology Inc.

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