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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 2082.75KB

  • 270頁(yè)

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
REGISTER 6-1:
R-0
OA
bit 15
R/W-0
(3)
IPL2
(2)
bit 7
Legend:
C = Clear only bit
S = Set only bit
鈥?鈥?= Bit is set
bit 7-5
R = Readable bit
W = Writable bit
鈥?鈥?= Bit is cleared
U = Unimplemented bit, read as 鈥?鈥?/div>
-n = Value at POR
x = Bit is unknown
R/W-0
(3)
IPL1
(2)
R/W-0
(3)
IPL0
(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
SR: CPU STATUS REGISTER
(1)
R-0
OB
R/C-0
SA
R/C-0
SB
R-0
OAB
R/C-0
SAB
R -0
DA
R/W-0
DC
bit 8
R/W-0
C
bit 0
IPL<2:0>:
CPU Interrupt Priority Level Status bits
(1)
111
= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110
= CPU Interrupt Priority Level is 6 (14)
101
= CPU Interrupt Priority Level is 5 (13)
100
= CPU Interrupt Priority Level is 4 (12)
011
= CPU Interrupt Priority Level is 3 (11)
010
= CPU Interrupt Priority Level is 2 (10)
001
= CPU Interrupt Priority Level is 1 (9)
000
= CPU Interrupt Priority Level is 0 (8)
For complete register details, see
Register 2-1: 鈥淪R: CPU Status Register鈥?
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> =
1.
User interrupts are disabled when
IPL<3> =
1.
The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) =
1.
Note 1:
2:
3:
REGISTER 6-2:
U-0
鈥?/div>
bit 15
R/W-0
SATA
bit 7
Legend:
R = Readable bit
0鈥?= Bit is cleared
bit 3
CORCON: CORE CONTROL REGISTER
(1)
U-0
鈥?/div>
U-0
鈥?/div>
R/W-0
US
R/W-0
EDT
R-0
R-0
DL<2:0>
R-0
bit 8
R/W-0
SATB
R/W-1
SATDW
R/W-0
ACCSAT
R/C-0
IPL3
(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
C = Clear only bit
W = Writable bit
鈥榵 = Bit is unknown
-n = Value at POR
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
IPL3:
CPU Interrupt Priority Level Status bit 3
(2)
1
= CPU interrupt priority level is greater than 7
0
= CPU interrupt priority level is 7 or less
For complete register details, see
Register 2-2: 鈥淐ORCON: CORE Control Register鈥?
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
Note 1:
2:
DS70290A-page 66
Preliminary
漏
2007 Microchip Technology Inc.

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