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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 270頁(yè)

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
5.1
Clock Source Selection at Reset
5.2
Device Reset Times
If clock switching is enabled, the system clock source at
device Reset is chosen as shown in Table 5-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to
Section 7.0 鈥淥scillator Configuration鈥?/span>
for
further details.
The Reset times for various types of device Reset are
summarized in Table 5-3. The system Reset signal,
SYSRST, is released after the POR and PWRT delay
times expire.
The time at which the device actually begins to execute
code also depends on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
TABLE 5-2:
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
Oscillator Configuration bits
(FNOSC<2:0>)
COSC Control bits
(OSCCON<14:12>)
Reset Type
POR
BOR
MCLR
WDTR
SWR
TABLE 5-3:
Reset Type
POR
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Clock Source
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
SYSRST Delay
T
POR
+ T
STARTUP
+ T
RST
T
POR
+ T
STARTUP
+ T
RST
T
POR
+ T
STARTUP
+ T
RST
T
POR
+ T
STARTUP
+ T
RST
T
STARTUP
+ T
RST
T
STARTUP
+ T
RST
T
STARTUP
+ T
RST
T
STARTUP
+ T
RST
T
RST
T
RST
T
RST
T
RST
T
RST
T
RST
System Clock
Delay
鈥?/div>
T
LOCK
T
OST
T
OST
+ T
LOCK
鈥?/div>
T
LOCK
T
OST
T
OST
+ T
LOCK
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
FSCM
Delay
鈥?/div>
T
FSCM
T
FSCM
T
FSCM
鈥?/div>
T
FSCM
T
FSCM
T
FSCM
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Notes
1, 2, 3
1, 2, 3, 5, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 5, 6
3
3, 5, 6
3, 4, 6
3, 4, 5, 6
3
3
3
3
3
3
BOR
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
2:
Any Clock
Any Clock
Any Clock
Any Clock
Any Clock
Any Clock
3:
4:
5:
6:
T
POR
= Power-on Reset delay (10
渭s
nominal).
T
STARTUP
= Conditional POR delay of 20
渭s
nominal (if on-chip regulator is enabled) or 64 ms nominal
Power-up Timer delay (if regulator is disabled). T
STARTUP
is also applied to all returns from powered-down
states, including waking from Sleep mode, only if the regulator is enabled.
T
RST
= Internal state Reset time (20
渭s
nominal).
T
OST
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.
T
LOCK
= PLL lock time (20
渭s
nominal).
T
FSCM
= Fail-Safe Clock Monitor delay (100
渭s
nominal).
DS70290A-page 58
Preliminary
漏
2007 Microchip Technology Inc.

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