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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 270頁

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
REGISTER 5-1:
bit 1
RCON: RESET CONTROL REGISTER
(1)
BOR:
Brown-out Reset Flag bit
1
= A Brown-out Reset has occurred
0
= A Brown-out Reset has not occurred
POR:
Power-on Reset Flag bit
1
= A Power-up Reset has occurred
0
= A Power-up Reset has not occurred
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is 鈥?鈥?(unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
bit 0
Note 1:
2:
TABLE 5-1:
RESET FLAG BIT OPERATION
Flag Bit
Setting Event
Trap conflict event
Illegal opcode or uninitialized
W register access
Configuration mismatch
MCLR Reset
RESET
instruction
WDT time-out
PWRSAV #SLEEP
instruction
PWRSAV #IDLE
instruction
BOR
POR
Clearing Event
POR, BOR
POR, BOR
POR, BOR
POR
POR, BOR
PWRSAV
instruction, POR, BOR,
CLRWDT
instruction
POR, BOR
POR, BOR
鈥?/div>
鈥?/div>
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
CM (RCON<9>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
Note:
All Reset flag bits may be set or cleared by the user software.
漏
2007 Microchip Technology Inc.
Preliminary
DS70290A-page 57

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