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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 2082.75KB

  • 270頁

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
REGISTER 5-1:
R/W-0
TRAPR
bit 15
R/W-0
EXTR
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
W = Writable bit
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
鈥?鈥?= Bit is cleared
x = Bit is unknown
R/W-0
SWR
R/W-0
SWDTEN
(2)
RCON: RESET CONTROL REGISTER
(1)
R/W-0
IOPUWR
U-0
鈥?/div>
U-0
鈥?/div>
U-0
鈥?/div>
U-0
鈥?/div>
R/W-0
CM
R/W-0
VREGS
bit 8
R/W-0
WDTO
R/W-0
SLEEP
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
bit 0
TRAPR:
Trap Reset Flag bit
1
= A Trap Conflict Reset has occurred
0
= A Trap Conflict Reset has not occurred
IOPUWR:
Illegal Opcode or Uninitialized W Access Reset Flag bit
1
= An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0
= An illegal opcode or uninitialized W Reset has not occurred
Unimplemented:
Read as 鈥?鈥?/div>
CM:
Configuration Mismatch Flag bit
1 = A configuration mismatch Reset has occurred.
0 = A configuration mismatch Reset has NOT occurred.
VREGS:
Voltage Regulator Standby During Sleep bit
1
= Voltage regulator is active during Sleep
0
= Voltage regulator goes into Standby mode during Sleep
EXTR:
External Reset (MCLR) Pin bit
1
= A Master Clear (pin) Reset has occurred
0
= A Master Clear (pin) Reset has not occurred
SWR:
Software Reset (Instruction) Flag bit
1
= A
RESET
instruction has been executed
0
= A
RESET
instruction has not been executed
SWDTEN:
Software Enable/Disable of WDT bit
(2)
1
= WDT is enabled
0
= WDT is disabled
WDTO:
Watchdog Timer Time-out Flag bit
1
= WDT time-out has occurred
0
= WDT time-out has not occurred
SLEEP:
Wake-up from Sleep Flag bit
1
= Device has been in Sleep mode
0
= Device has not been in Sleep mode
IDLE:
Wake-up from Idle Flag bit
1
= Device was in Idle mode
0
= Device was not in Idle mode
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is 鈥?鈥?(unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
bit 14
bit 13-10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Note 1:
2:
DS70290A-page 56
Preliminary
漏
2007 Microchip Technology Inc.

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