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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 2082.75KB

  • 270頁(yè)

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
5.0
Note:
RESETS
This data sheet summarizes the features
of the dsPIC33FJ32GP202/204 and
dsPIC33FJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the
鈥渄sPIC33F
Family Reference Manual鈥?
Any active source of Reset makes the SYSRST signal
active. Many registers associated with the CPU and
peripherals are forced to a known Reset state. Most
registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
POR: Power-on Reset
BOR: Brown-out Reset
MCLR: Master Clear Pin Reset
SWR:
RESET
Instruction
WDTO: Watchdog Timer Reset
TRAPR: Trap Conflict Reset
IOPUWR: Illegal Opcode, Uninitialized W Regis-
ter Reset, and Security Reset
鈥?CM: Configuration Mismatch Reset
A simplified block diagram of the Reset module is
shown in Figure 5-1.
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All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 5-1). A POR will clear all bits, except for
the POR bit (RCON<0>), that are set. The user appli-
cation can set or clear any bit at any time during code
execution. The RCON bits only serve as status bits.
Setting a particular Reset status bit in software does
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
FIGURE 5-1:
RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
SYSRST
POR
V
DD
Internal
Regulator
V
DD
Rise
Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
Configuration Mismatch
漏
2007 Microchip Technology Inc.
Preliminary
DS70290A-page 55

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