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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 270頁(yè)

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
REGISTER 4-1:
R/SO-0
(1)
WR
bit 15
U-0
鈥?/div>
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
SO = Satiable only bit
W = Writable bit
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
鈥?鈥?= Bit is cleared
x = Bit is unknown
R/W-0
(1)
ERASE
U-0
鈥?/div>
U-0
鈥?/div>
R/W-0
(1)
R/W-0
(1)
R/W-0
(1)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0
(1)
WRERR
U-0
鈥?/div>
U-0
鈥?/div>
U-0
鈥?/div>
U-0
鈥?/div>
U-0
鈥?/div>
bit 8
R/W-0
(1)
bit 0
WREN
R/W-0
(1)
NVMOP<3:0>
(2)
WR:
Write Control bit
1
= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete.
0
= Program or erase operation is complete and inactive
WREN:
Write Enable bit
1
= Enable Flash program/erase operations
0
= Inhibit Flash program/erase operations
WRERR:
Write Sequence Error Flag bit
1
= An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0
= The program or erase operation completed normally
Unimplemented:
Read as 鈥?鈥?/div>
ERASE:
Erase/Program Enable bit
1
= Perform the erase operation specified by NVMOP<3:0> on the next WR command
0
= Perform the program operation specified by NVMOP<3:0> on the next WR command
Unimplemented:
Read as 鈥?鈥?/div>
NVMOP<3:0>:
NVM Operation Select bits
(2)
If ERASE =
1:
1111
= Memory bulk erase operation
1101
= Erase General Segment
1100
= Erase Secure Segment
0011
= No operation
0010
= Memory page erase operation
0001
= No operation
0000
= Erase a single Configuration register byte
If ERASE =
0:
1111
= No operation
1101
= No operation
1100
= No operation
0011
= Memory word program operation
0010
= No operation
0001
= Memory row program operation
0000
= Program a single Configuration register byte
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-0
Note 1:
2:
These bits can only be reset on POR.
All other combinations of NVMOP<3:0> are unimplemented.
漏
2007 Microchip Technology Inc.
Preliminary
DS70290A-page 51

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