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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 270頁

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
Communication Modules:
鈥?4-wire SPI:
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
2
C鈩?
鈥?I
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
鈥?UART:
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA
廬
encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
Analog-to-Digital Converters (ADCs):
鈥?10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- 2 and 4 simultaneous samples (10-bit ADC)
- Up to 13 input channels with auto-scanning
- Conversion start can be manual or
synchronized with 1 of 4 trigger sources
- Conversion possible in Sleep mode
- 鹵2 LSb max integral nonlinearity
- 鹵1 LSb max differential nonlinearity
CMOS Flash Technology:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Low-power, high-speed Flash technology
Fully static design
3.3V (鹵10%) operating voltage
Industrial and extended temperature
Low-power consumption
Packaging:
鈥?28-pin SPDIP/SOIC/QFN-S
鈥?44-pin QFN/TQFP
Note:
See the device variant tables for exact
peripheral features per device.
DS70290A-page 2
Preliminary
漏
2007 Microchip Technology Inc.

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