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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 270頁

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
2.5
Arithmetic Logic Unit (ALU)
The
dsPIC33FJ32GP202/204
and
dsPIC33FJ16GP304 ALU is 16 bits wide and is capa-
ble of addition, subtraction, bit shifts and logic opera-
tions. Unless otherwise mentioned, arithmetic
operations are 2鈥檚 complement in nature. Depending
on the operation, the ALU can affect the values of the
Carry (C), Zero (Z), Negative (N), Overflow (OV) and
Digit Carry (DC) Status bits in the SR register. The C
and DC Status bits operate as Borrow and Digit Borrow
bits, respectively, for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The
dsPIC33FJ32GP202/204
and
dsPIC33FJ16GP304 CPU incorporates hardware sup-
port for both multiplication and division. This includes a
dedicated hardware multiplier and support hardware
for 16-bit-divisor division.
Refer to the 鈥渄sPIC30F/33F
Programmer鈥檚 Reference
Manual鈥?/div>
(DS70157) for information on the SR bits
affected by each instruction.
1.
2.
3.
4.
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV
instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m+1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
2.6
DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
is a single-cycle instruction flow architecture; therefore,
concurrent operation of the DSP engine with MCU
instruction flow is not possible. However, some MCU
ALU and DSP engine resources can be used concur-
rently by the same instruction (e.g., ED, EDAC).
The DSP engine can also perform accumula-
tor-to-accumulator operations that require no additional
data. These instructions are
ADD, SUB
and
NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
Fractional or integer DSP multiply (IF)
Signed or unsigned DSP multiply (US)
Conventional or convergent rounding (RND)
Automatic saturation on/off for AccA (SATA),
AccB (SATB) and writes to data memory
(SATDW)
鈥?Accumulator Saturation mode selection
(ACCSAT)
A block diagram of the DSP engine is shown in
Figure 2-3.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
2.5.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the DSP
engine, the ALU supports unsigned, signed or mixed-sign
operation in several MCU multiplication modes:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
2.5.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
TABLE 2-1:
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
DSP INSTRUCTIONS SUMMARY
Algebraic Operation
A=0
A = (x 鈥?y)
2
A = A + (x 鈥?y)
2
A = A + (x * y)
A = A + x
2
No change in A
A=x*y
A=x
2
A=鈥搙*y
A=A鈥搙*y
ACC Write Back
Yes
No
No
Yes
No
Yes
No
No
No
Yes
Instruction
漏
2007 Microchip Technology Inc.
Preliminary
DS70290A-page 19

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