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dsPIC33FJ32GP204 Datasheet

  • dsPIC33FJ32GP204

  • High-Performance,16-bit Digital Signal Controllers

  • 270頁(yè)

  • Microchip   Microchip

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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
TABLE 1-1:
Pin Name
AN0-AN12
CLKI
CLKO
PINOUT I/O DESCRIPTIONS
Pin Type
I
I
O
Buffer Type
Analog
ST/CMOS
鈥?/div>
Analog input channels.
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
32.768 kHz low-power oscillator crystal input; CMOS otherwise.
32.768 kHz low-power oscillator crystal output.
Change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
Capture inputs 1/2
Capture inputs 7/8
Compare Fault A input (for Compare Channels 1 and 2).
Compare outputs 1 through 2.
External interrupt 0.
External interrupt 1.
External interrupt 2.
PORTA is a bidirectional I/O port.
PORTB is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
CPU logic filter capacitor connection.
Ground reference for logic and I/O pins.
Analog voltage reference (high) input.
Analog voltage reference (low) input.
Description
OSC1
OSC2
SOSCI
SOSCO
CN0-CN30
IC1-IC2
IC7-IC8
OCFA
OC1-OC2
INT0
INT1
INT2
RA0-RA4
RA7-RA15
RB0-RB15
RC0-RC9
T1CK
T2CK
T3CK
U1CTS
U1RTS
U1RX
U1TX
SCK1
SDI1
SDO1
SS1
SCL1
SDA1
ASCL1
ASDA1
TMS
TCK
TDI
TDO
PGD1/EMUD1
PGC1/EMUC1
PGD2/EMUD2
PGC2/EMUC2
PGD3/EMUD3
PGC3/EMUC3
V
DDCORE
V
SS
V
REF
+
V
REF
-
I
I/O
I
O
I
I
I
O
I
I
I
I/O
I/O
I/O
I
I
I
I
O
I
O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
I/O
I
I/O
I
I/O
I
P
P
I
I
ST/CMOS
鈥?/div>
ST/CMOS
鈥?/div>
ST
ST
ST
鈥?/div>
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
鈥?/div>
ST
鈥?/div>
ST
ST
鈥?/div>
ST
ST
ST
ST
ST
ST
ST
ST
鈥?/div>
ST
ST
ST
ST
ST
ST
鈥?/div>
鈥?/div>
Analog
Analog
Legend:
CMOS = CMOS compatible input or output; Analog = Analog input
ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power
漏
2007 Microchip Technology Inc.
Preliminary
DS70290A-page 11

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